DS31256 datasheet(141/183 Pages) MAXIM

141 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

141 of 183

PDCM

PCI Device Configuration Memory Base Address Register

0x010h

LSB

Base Address (Read Only/Set to 0h)

TYPE1

TYPE0

MSI

Base Address

Base Address (Read Only/Set to 0h)

Base Address

MSB

Base Address

Note: Read-only bits in the PDCM register are underlined; all other bits are read-write.

Bit 0/Memory Space Indicator (MSI). This read-only bit is forced to 0 to indicate that the internal device

configuration registers are mapped to memory space.

Bits 1, 2/Type 0, Type 1. These read-only bits are forced to 00b to indicate that the internal device configuration

registers can be mapped anywhere in the 32-bit address space.

Bit 3/Prefetchable (PF). This read-only bit is forced to 0 to indicate that prefetching is not supported by the

device for the internal device configuration registers.

Bits 4 to 11/Base Address. These read-only bits are forced to 0 to indicate that the internal device configuration

registers require 4kB of memory space.

Bits 12 to 31/Base Address. These read/write bits define the location of the 4kB memory space that is mapped to

the internal configuration registers. These bits correspond to the most significant bits of the PCI address space.

PINTL0

PCI Interrupt Line and Pin/Minimum Grant/Maximum Latency Register 0

0x03Ch

LSB

Interrupt Line

Interrupt Pin (Read Only/Set to 01h)

Maximum Grant (Read Only/Set to 05h)

MSB

Maximum Latency (Read Only/Set to 0 Fh)

Bits 0 to 7/Interrupt Line. These read/write bits indicate and store interrupt line routing information. The device

does not use this information, it is only posted here for the host to use.

Bits 8 to 15/Interrupt Pin. These read-only bits are forced to 01h to indicate that

PINTA is used as an interrupt.

Bits 16 to 23/Minimum Grant. These read-only bits are used to indicate to the host how long of a burst period

the device needs, assuming a clock rate of 33MHz. The values placed in these bits specify a period of time in

0.25

µs increments. These bits are forced to 05h.

Bits 24 to 31/Maximum Latency. These read-only bits are used to indicate to the host how often the device needs

to gain access to the PCI bus. The values placed in these bits specify a period of time in 0.25

µs increments. These

bits are forced to 0Fh.

DS31256 数据表(PDF) 141 Page - Maxim Integrated Products

DS31256 数据表(HTML) 141 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DS31256 数据表(PDF) 141 Page - Maxim Integrated Products

DS31256 数据表(HTML) 141 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载