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DS31256 数据表(PDF) 164 Page - Maxim Integrated Products |
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DS31256 数据表(HTML) 164 Page - Maxim Integrated Products |
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164 / 183 page ![]() DS31256 256-Channel, High-Throughput HDLC Controller 164 of 183 12.2 TAP Controller State Machine Description This section details the operation of the TAP controller state machine. See Figure 12-2 for details about each of the states. The TAP controller is a finite state machine, which responds to the logic level at JTMS on the rising edge of JTCLK. Figure 12-2. TAP Controller State Machine Test-Logic-Reset Run-Test/Idle Select DR-Scan 1 0 Capture-DR 1 0 Shift-DR 0 1 Exit1-DR 1 0 Pause-DR 1 Exit2-DR 1 Update-DR 0 0 1 Select IR-Scan 1 0 Capture-IR 0 Shift-IR 0 1 Exit1-IR 1 0 Pause-IR 0 Exit2-IR 1 Update-IR 0 0 1 0 0 1 0 1 0 1 |
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