EDBA164B4PR-1DATF-R datasheet(137/152 Pages) MICRON

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OL + 2x X mV

OL + X mV

OH - X mV

OH - 2x X mV

2x X

2x Y

T1 T2

TT - Y mV

TT - 2x Y mV

TT + 2x Y mV

TT + Y mV

tLZ(DQS), tLZ(DQ)

tHZ(DQS), tHZ(DQ)

T1 T2

Start driving point = 2 × T1 - T2

End driving point = 2 × T1 - T2

actual wave

7. Measured from the point when DQS_t/DQS_c begins driving the signal, to the point

when DQS_t/DQS_c begins driving the first rising strobe edge.

8. Measured from the last falling strobe edge of DQS_t/DQS_c to the point when DQS_t/

DQS_c finishes driving the signal.

9. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to

CK_t/CK_c crossing.

10. CKE input hold time is measured from CK_t/CK_n crossing to CKE reaching a HIGH/LOW

voltage level.

11. Input setup/hold time for signal (CA[9:0], CS_n).

12. To ensure device operation before the device is configured, a number of AC boot timing

parameters are defined in this table. The letter b is appended to the boot parameter

symbols (for example, tCK during boot is tCKb).

13. Mobile LPDDR2 devices set some mode register default values upon receiving a RESET

(MRW) command, as specified in Mode Register Definition.

14. The output skew parameters are measured with default output impedance settings

using the reference load.

15. The minimum tCK column applies only when tCK is greater than 6ns.

16. Timing derating applies for operation at 85˚C to 105˚C when the requirement to derate

is indicated by mode register 4 op-code (see the MR4 Device Temperature (MA[7:0] =

04h) table).

17. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-

cesses to a particular row address may result in reduction of the product lifetime.

CA and CS_n Setup, Hold, and Derating

For all input signals (CA and CS_n), the total required setup time (tIS) and hold time

(tIH) are calculated by adding the data sheet tIS (base) and tIH (base) values to the ΔtIS

and ΔtIH derating values, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.

(See the series of tables following this section.)

The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the

last crossing of VREF(DC) and the first crossing of VIH(AC)min. The typical setup slew rate

for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and

the first crossing of VIL(AC)max. If the actual signal is consistently earlier than the typical

slew rate line between the shaded VREF(DC)-to-(AC) region, use the typical slew rate for

the derating value (see Figure 83 (page 141)). If the actual signal is later than the typical

slew rate line anywhere between the shaded VREF(DC)-to-AC region, the slew rate of a

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

CA and CS_n Setup, Hold, and Derating

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

137

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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