EDBA164B4PR-1DATF-R datasheet(138/152 Pages) MICRON

138 / 152 page

tangent line to the actual signal from the AC level to the DC level is used for the derating

value (see Figure 85 (page 143)).

The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the

last crossing of VIL(DC)max and the first crossing of VREF(DC). The hold (tIH) typical slew

rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min

and the first crossing of VREF(DC). If the actual signal is consistently later than the typical

slew rate line between the shaded DC-to-VREF(DC) region, use the typical slew rate for

the derating value (see Figure 84 (page 142)). If the actual signal is earlier than the typi-

cal slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a

tangent line to the actual signal from the DC level to VREF(DC) level is used for the derat-

ing value (see Figure 86 (page 144)).

For a valid transition, the input signal must remain above or below VIH/VIL(AC) for a

specified time, tVAC (see Table 96 (page 139)).

For slow slew rates the total setup time could be a negative value; that is, a valid input

signal will not have reached VIH/VIL(AC) at the time of the rising clock transition. A valid

input signal is still required to complete the transition and reach VIH/VIL(AC).

For slew rates between the values listed in Table 94, the derating values are obtained us-

ing linear interpolation. Typically, slew rate values are not subject to production testing.

They are verified by design and characterization.

Table 92: CA and CS_n Setup and Hold Base Values (>400 MHz, 1 V/ns Slew Rate)

Parameter

Data Rate

Reference

1066

933

800

667

533

466

tIS (base)

150

240

300

VIH/VIL(AC) = VREF(DC) ±220mV

tIH (base)

120

160

240

330

390

VIH/VIL(DC) = VREF(DC) ±130mV

Note:

1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c

slew rate.

Table 93: CA and CS_n Setup and Hold Base Values (<400 MHz, 1 V/ns Slew Rate)

Parameter

Data Rate

Reference

400

333

266

200

tIS (base)

300

440

600

850

VIH/VIL(AC) = VREF(DC) ±300mV

tIH (base)

400

540

700

950

VIH/VIL(DC) = VREF(DC) ±200mV

Note:

1. AC/DC referenced for 1 V/ns CA and CS_n slew rate, and 2 V/ns differential CK_t/CK_c

slew rate.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

CA and CS_n Setup, Hold, and Derating

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

138

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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