MPFS250T datasheet(18/128 Pages) MICROCHIP

18 / 128 page

5. VDDIx is powered down and the device is driven to –0.3 V < VIN < GPIO VDDImax.

Note: The following dedicated pins do not support hot socketing: TMS, TDI, TRSTB, and DEVRST_N. Weak

pull-up (as specified in GPIO) is always enabled.

5.3

Input and Output

The following section describes DC I/O levels, differential and complementary differential DC I/O levels,

HSIO and GPIO on-die termination specifications, and LVDS specifications.

5.3.1

DC Input and Output Levels

The following tables list the DC I/O levels.

Table 14 • DC Input Levels

VIH

Max (V)

VIH

Min (V)

VIL

Max (V)

VIL

Min (V)

VDDI

Max (V)

VDDI

Typ (V)

VDDI

Min (V)

I/O Standard

3.45

0.5 × VDDI

0.3 × VDDI

–0.3

3.45

3.3

3.15

PCI

3.45

0.8

–0.3

3.45

3.3

3.15

LVTTL

3.45

0.8

–0.3

3.45

3.3

3.15

LVCMOS33

2.625

1.7

0.7

–0.3

2.625

2.5

2.375

LVCMOS25

1.89

0.65 × VDDI

0.35 × VDDI

–0.3

1.89

1.8

1.71

LVCMOS18

1.575

0.65 × VDDI

0.35 × VDDI

–0.3

1.575

1.5

1.425

LVCMOS15

1.26

0.65 × VDDI

0.35 × VDDI

–0.3

1.26

1.2

1.14

LVCMOS12

2.625

VREF + 0.15

VREF – 0.15

–0.3

2.625

2.5

2.375

SSTL25I

2.625

VREF + 0.15

VREF – 0.15

–0.3

2.625

2.5

2.375

SSTL25II

1.89

VREF + 0.125

VREF – 0.125

–0.3

1.89

1.8

1.71

SSTL18I

1.89

VREF + 0.125

VREF – 0.125

–0.3

1.89

1.8

1.71

SSTL18II

1.575

VREF + 0.1

VREF – 0.1

–0.3

1.575

1.5

1.425

SSTL15I

1.575

VREF + 0.1

VREF – 0.1

–0.3

1.575

1.5

1.425

SSTL15II

1.418

VREF + 0.09

VREF – 0.09

–0.3

1.418

1.35

1.283

SSTL135I

1.418

VREF + 0.09

VREF – 0.09

–0.3

1.418

1.35

1.283

SSTL135II

1.575

VREF + 0.1

VREF – 0.1

–0.3

1.575

1.5

1.425

HSTL15I

1.575

VREF + 0.1

VREF – 0.1

–0.3

1.575

1.5

1.425

HSTL15II

1.418

VREF + 0.09

VREF – 0.09

–0.3

1.418

1.35

1.283

HSTL135I

1.418

VREF + 0.09

VREF – 0.09

–0.3

1.418

1.35

1.283

HSTL135II

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

DC Characteristics

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