MPFS250T datasheet(64/128 Pages) MICROCHIP

64 / 128 page

Jtolmin (UI)

Max Tx to Rx Fre-

quency Offset

(ppm)

Max Data Rate (M-

bps)

Min Data Rate (M-

bps)

I/O Configuration

Buffer Type

0.1

±100

1250

266

LVDS18

HSIO

1, 2

0.1

±100

1250

266

LVDS25

GPIO

1, 3

1. Jitter tolerance of applied sinusoidal jitter from 1 KHz to 120 MHz, as shown in figure LVDS Jitter Tolerance

Plot. It is measured in addition to a stressed eye of Tj= 0.24 UI with VICM of 1.25 V and VIDmin of 250 mV,

with the CDR operating at a rate of 1250 Mbps plus or minus the ppm offset listed.

2. HSIO LVDS uses an external 100 Ω differential termination resistor. For more information, see LVDS

specification in table Differential DC Input Levels.

3. GPIO LVDS uses an internal 100 Ω differential termination resistor. For more information, see LVDS

specification in table Differential DC Input Levels.

6.3

Clocking Specifications

This section describes the PLL and DLL clocking and oscillator specifications.

6.3.1

Clocking

The following table describes clocking specifications.

Table 71 • Global and Regional Clock Characteristics (–40 °C to 100 °C)

Condition

Unit

V DD = 1.05 V

–1

V DD = 1.05 V

STD

V DD = 1.0 V

–1

V DD= 1.0 V S-

Symbol

Parameter

MHz

500

FMAXG

Global clock

FMAX

Transceiver

interfaces on-

MHz

375

FMAXR

Regional

clock FMAX

All other inter-

faces

MHz

250

FMAXR

At 500 MHz

190

TDCDG

Global clock

duty cycle dis-

tortion

At 250 MHz

120

TDCDR

Regional

clock duty cy-

cle distortion

The following table describes clocking specifications from –40 °C to 100 °C.

Table 72 • High-Speed I/O Clock Characteristics (–40 °C to 100 °C)

Condition

Unit

VDD = 1.05 V

–1

VDD = 1.05 V

STD

VDD= 1.0 V –1

VDD= 1.0 V ST-

Symbol

Parameter

HSIO and GPI-

MHz

1250

1000

1250

1000

FMAXB

High-speed I/

O clock FMAX

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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