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MPFS250T 数据表(PDF) 62 Page - Microchip Technology |
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MPFS250T 数据表(HTML) 62 Page - Microchip Technology |
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62 / 128 page  Forwarded Clock-to-D- ata Skew –1 (Mbps) STD (Mbps) –1 (MHz) STD (MHz) I/O Type Topology Interface N- ame Parameter source, aligned From a global clock 1000 1000 500 500 HSIO, GPIO Tx DDR TX_DDR_G_ C source, cen- tered From a HS_ IO_CLK 1000 800 500 400 HSIO Tx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 2:1 clock source, aligned From a HS_ IO_CLK 1600 1333 800 667 HSIO Tx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 4:1 Output FMA- X 5:1 clock source, aligned From a HS_ IO_CLK 1000 800 500 400 HSIO Tx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 2:1 clock source, cen- tered with PLL From a HS_ IO_CLK 1600 1333 800 667 HSIO Tx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 4:1 Output FMA- X 5:1 clock source, cen- tered with PLL From a HS_ IO_CLK 1000 800 500 400 GPIO Tx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 2:1 clock source, aligned From a HS_ IO_CLK 1600 1250 800 625 GPIO Tx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 4:1 Output FMA- X 5:1 clock source, aligned From a HS_ IO_CLK 1000 800 500 400 GPIO Tx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 2:1 clock source, cen- tered with PLL From a HS_ IO_CLK 1600 1250 800 625 GPIO Tx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 4:1 Output FMA- X 5:1 clock source, cen- tered with PLL 58 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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