MPFS250T datasheet(86/128 Pages) MICROCHIP

86 / 128 page

Condition

Unit

Max

Typ

Min

Symbol

Parameter

12.7 Gbps

6, 11

0.05

0.1

CTLE DC gain (all

stages, max set-

tings)

0.05

CTLE AC gain (all

stages, max set-

tings)

7.5

0.05

DFE AC gain (per

5 stages, max

settings)

TCTLE

Auto adaptive

calibration time

(CTLE)

1.4

TCTLE+DFE

Auto adaptive

calibration time

(CTLE+DFE)

MHz

41.6

38.4

FERMCTRLCLK

Enhanced receiv-

er mangement

control clock in-

put (CTRL_CLK)

1. Valid at 3.2 Gbps and below.

2. Data vs Rx reference clock frequency.

3. Achieves compliance with PCIe electrical idle detection.

4. Achieves compliance with SATA OOB specification.

5. Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of

Rx CTLE enabled, DFE disabled, 80 MHz sinusoidal jitter injected to Rx data.

6. Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of

Rx CTLE enabled, DFE enabled, 80 MHz sinusoidal jitter injected to Rx data.

7. For PCIe: Low Threshold Setting= 0, High Threshold Setting= 2.

8. For SATA: Low Threshold Setting= 2, High Threshold Setting= 3.

9. Loss of signal is valid for data rates of 1 Gbps to 5 Gbps for PRBS7 (8B/10B) or PRBS31 (64b/6xb) data

formats. It is also valid for detection of SATA out-of-band signals at data rates up to 6 Gbps. If the default

settings for the low threshold (0x0) and high threshold (0x2) using the low range option for the peak

detector are used, then the Rx VAmplitude pk-pk (outside of data eye) at the receiver input package pins

must be a minimum of 300 mV for short reach (6.5 dB insertion loss at 5 GHz) applications, 350 mV for

medium reach (17.0 dB insertion loss at 5 GHz) applications, and 450 mV for long reach (25.0 dB insertion

loss at 5 GHz) applications—generally the settings are less limiting than what is required for good BER

operation of the SerDes. Note that if the option to force CDR Lock2Ref upon Rx Idle is set (default at

data rates of 5 Gbps and below), this minimum VAmplitude pk-pk must be enforced for proper CDR

operation.

10. Detect values measured at 1.5 Gbps with PRBS7 data pattern.

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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