MPFS250T datasheet(61/128 Pages) MICROCHIP

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Clock-to-D-

ata Condi-

tion

–1 (Mbps)

STD (Mbps)

–1 (MHz)

STD (MHz)

I/O Type

Topology

Interface N-

ame

Parameter

gional fab-

ric clock

From a HS_

IO_CLK

540

440

270

220

HSIO

Rx DDR digi-

tal mode

RX_DDRX_

B_R_A

Input FMAX

4:1 Input

FMAX 5:1

500

410

250

205

GPIO

clock

source,

aligned, re-

gional fab-

ric clock

From a HS_

IO_CLK

540

440

270

220

HSIO

Rx DDR digi-

tal mode

RX_DDRX_

B_R_C

Input FMAX

2:1

500

410

250

205

GPIO

clock

source, cen-

tered, re-

gional fab-

ric clock

From a HS_

IO_CLK

540

440

270

220

HSIO

Rx DDR digi-

tal mode

RX_DDRX_

B_R_C

Input FMAX

4:1 Input

FMAX 5:1

500

410

250

205

GPIO

clock

source, cen-

tered, re-

gional fab-

ric clock

1. VID ≥ 200 mV, VICM ≥100 mV, Tj=0.4 UI.

2. A centered clock-to-data interface can be created with a negedge launch of the data.

Table 67 • I/O Digital Transmit Single Data Rate Switching Characteristics

Forwarded

Clock-to-D-

ata Skew

–1 (Mbps)

STD (Mbps)

–1 (MHz)

STD (MHz)

I/O Type

Topology

Interface N-

ame

Parameter

From a

global clock

500

HSIO, GPIO

Tx SDR

TX_SDR_G_

Output FMA-

source,

aligned

From a

global clock

500

HSIO, GPIO

Tx SDR

TX_SDR_G_

source, cen-

tered

1. A centered clock-to-data interface can be created with a negedge launch of the data.

Table 68 • I/O Digital Transmit Double Data Rate Switching Characteristics

Forwarded

Clock-to-D-

ata Skew

–1 (Mbps)

STD (Mbps)

–1 (MHz)

STD (MHz)

I/O Type

Topology

Interface N-

ame

Parameter

From a

global clock

1000

500

HSIO, GPIO

Tx DDR

TX_DDR_G_

Output FMA-

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

MPFS250T 数据表(PDF) 61 Page - Microchip Technology

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MPFS250T 数据表(PDF) 61 Page - Microchip Technology

MPFS250T 数据表(HTML) 61 Page - Microchip Technology

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