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MPFS250T 数据表(PDF) 76 Page - Microchip Technology |
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MPFS250T 数据表(HTML) 76 Page - Microchip Technology |
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76 / 128 page ![]() Unit –1 Max –1 Typ –1 Min STD Max STD Typ STD Min Symbol Parameter KHz TxREF CLKP- FD/ (128*6 3) 32 TxREF CLKP- FD/ (128) TxREF CLKP- FD/ (128*6 3) 32 TxREF CLKP- FD/ (128) Mod_Freq Spread spectrum modulation frequency 7 1. See the maximum reference clock rate allowed per input buffer standard. 2. The minimum value applies to this clock when used as an XCVR reference clock. It does not apply when used as a non-XCVR input buffer (DC input allowed). 3. Cascaded reference clock. 4. After reference clock input divider. 5. To calculate the FTXREFPN phase noise requirement at frequencies other than 156 MHz use the following formula: FTXREFPN at f(MHz) = FTXREFPN at 156 MHz + 20*log(f/156) 6. Programmable capability for depth of down-spread or center-spread modulation. 7. Programmable modulation rate based on the modulation divider setting (1 to 63). 6.5.3 Transceiver Reference Clock I/O Standards The following differential I/O standards are supported as transceiver reference clocks. • LVDS25/33 • HCLS25 (for PCIe) • RSDS25/33 • MINILVDS25/33 • SUBLVDS25/33 • PPDS25/33 • SLVS25/33 • BUSLVDS25 • MLVDS25 • LVPECL33 • MIPI25 For DC input levels, see table Differential DC Input and Output Levels. Note: The transceiver reference clock differential receiver supports VICM common mode. Note: The amount of jitter from the input receiver increases at common modes of less 0.2 V or greater than VDDSREF–0.4 V. Therefore, for improved SerDes operation, it is recommended that the VCM of the signal into the SerDes reference clock input be at a minimum of 0.2 V and below VDDSREF–0.4 V. The following single-ended I/O standards are supported as transceiver reference clocks. • LVTTL • LVCMOS33 • LVCMOS25 • LVCMOS18 • SSTL25I/II • SSTL18I/II • HSUL18I/II 72 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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