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MPFS250T 数据表(PDF) 36 Page - Microchip Technology |
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MPFS250T 数据表(HTML) 36 Page - Microchip Technology |
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36 / 128 page  Table 37 • SD/SDIO Interface High-Speed Mode Units Max Typ Min Symbol Parameter % 53 47 TDCSDHSCLK SD device clock du- ty cycle ns 13.8 2.2 TSDHSCKO Clock to output de- lay, all outputs UI 0.4 TSDHSDIVW Input valid data window MHz 50 FSDHSCLK High-speed mode SD device clock fre- quency Table 38 • SD/SDIO Interface Standard Mode Units Max Typ Min Symbol Parameter % 55 45 TDCSDHSCLK SD device clock du- ty cycle ns 4.5 –2.0 TSDSCKO Clock to output de- lay, all outputs ns 2.0 TSDSDCK Input setup time, all inputs ns 2.0 TSDSCKD Input hold time, all inputs KHz 400 FSDIDCLK Clock frequency in identification mode MHz 19 FSDSCLK Standard SD device clock frequency 6.1.6 eMMC The following tables describe the eMMC. The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load (I/O voltage of 3 V/1.8 V/1.2 V). For eMMC high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and 30 pF load (I/O voltage of 3 V/1.8 V/1.2 V). For other eMMC modes, the test conditions use a 12 mA drive strength, fast slew rate, and 15 pF load (I/O voltage of 1.8 V/1.2 V) Table 39 • eMMC Standard Interface Units Max Typ Min Symbol Parameter % 55 45 TDCEMMCHSCLK eMMC clock duty cycle ns 4.5 –2.0 TEMMCHSCKO Clock to output de- lay, all outputs ns 2.0 TEMMCHSDCK Input setup time, all inputs 32 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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