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MPFS250T 数据表(PDF) 41 Page - Microchip Technology |
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MPFS250T 数据表(HTML) 41 Page - Microchip Technology |
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41 / 128 page  Table 50 • Feedback Clock Enabled or Disabled Units Max Min Load Conditions Symbol Parameter MHz 150 All 1, 2 FQSPI_REF_CLK Quad-SPI reference clock frequency 6.1.11 SPI The following tables describes the SPI master and slave mode switching characteristics. The test conditions are configured to the LVCMOS 3.3 V I/O standard with a 12 mA drive strength, fast slew rate, and a 30 pF load. Table 51 • SPI Master Mode Switching Characteristics Units Max Min Symbol Parameter % 55 45 TDCMSPICLK SPI master mode clock duty cycle FSPI_REF_CLK cycles 1.0 TMSPISSCLK Slave select asserted to first active clock edge FSPI_REF_CLK cycles 1.0 TMSPICLKSS Last active clock edge to slave select deasserted ns –2.0 TMSPIDCK Input setup time for MI- SO ns 0.3 TMSPICKD Input hold time for MIS- O ns 5.0 –2.0 TMSPICKO MOSI and slave select clock to out delay MHz 50 FMSPICLK SPI master mode device clock frequency MHz 150 FSPI_REF_CLK SPI reference clock fre- quency Table 52 • SPI Slave Mode Switching Characteristics Units Max Min Symbol Parameter FSPI_REF_CLK cycles 2.0 TSSPISSCLK Slave select asserted to first active clock edge FSPI_REF_CLK cycles 2.0 TSSPICLKSS Last active clock edge to slave select deasserted ns 5.0 TSSPIDCK Input setup time for M- OSI ns 1.0 TSSPICKD Input hold time for MO- SI ns 13.0 0.0 TSSPIOCK MISO clock to out delay 37 Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics |
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