MPFS250T datasheet(58/128 Pages) MICROCHIP

58 / 128 page

Unit

–1

STD

Standard

Mbps

300

250

LVCMOS12 (8 mA)

Mbps

1000

MIPIE25

Note: LVDS25 configuration should be used when implementing SGMII transmitters.

6.2.5

Maximum PHY Rate for FPGA Memory Interface IP

The following tables describe the maximum PHY rate for FPGA memory interface IP.

Table 63 • Maximum PHY Rate for FPGA Memory Interfaces IP for HSIO Banks

Fabric –1 (M-

Hz)

Fabric STD

(MHz)

–1 (Mbps)

STD (Mbps)

VDDI

VDDAUX

Gearing Ratio

MemoryStan-

dard

200

167

1600

1333

1.2 V

1.8 V

8:1

DDR4

167

133

1333

1067

1.5 V

1.8 V

8:1

DDR3

167

133

1333

1067

1.35 V

1.8 V

8:1

DDR3L

167

133

1333

800

1.2 V

1.8 V

8:1

LPDDR3

137.5

112.5

1100

900

1.5 V

1.8 V

8:1

QDRII+

133

1067

1.35 V

1.8 V

8:1

RLDRAM3

200

167

800

667

1.35 V

1.8 V

4:1

RLDRAM3

200

167

400

333

1.35 V

1.8 V

2:1

RLDRAM3

133

100

1067

800

1.8 V

8:1

RLDRAMII

200

167

800

667

1.8 V

4:1

RLDRAMII

200

167

400

333

1.8 V

2:1

RLDRAMII

1. Simulation data only. Microchip does not provide a soft controller for RLDRAMII, RLDRAM3, or DDR3L.

2. Simulation data only. RLDRAMII is currently not supported with a soft IP controller.

Table 64 • Maximum PHY Rate for FPGA Memory Interfaces IP for GPIO Banks

Fabric –1 (M-

Hz)

Fabric STD

(MHz)

–1 (Mbps)

STD (Mbps)

VDDI

VDDAUX

Gearing Ratio

MemoryStan-

dard

133

100

1067

800

1.5 V

2.5 V

8:1

DDR3

113

900

1.5 V

2.5 V

8:1

QDRII+

200

800

1.8 V

2.5 V

4:1

RLDRAMII

200

400

1.8 V

2.5 V

2:1

RLDRAMII

1. Simulation data only. RLDRAMII is currently not supported with a soft IP controller.

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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