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CS5535 数据表(PDF) 247 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 247 Page - National Semiconductor (TI) |
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247 / 555 page  Revision 0.8 247 www.national.com 5.4 ATA-5 CONTROLLER REGISTER DESCRIPTIONS The control registers for the ATA-5 compatible IDE control- ler (ATAC) are divided into three sets: • Standard GeodeLink Device MSRs • ATAC Specific MSRs • ATAC Native Registers The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. The Native registers are accessed as I/O Offsets from a GLIU IOD Descriptor and are BYTE, WORD and DWORD accessible. Tables 5-10 through 5-12 are ATAC register summary tables that include reset values and page references where the bit descriptions are provided. Table 5-10. Standard GeodeLink Device MSRs Summary MSR Address Type Register Name Reset Value Reference 51300000h RO GeodeLink Device Capabilities MSR (ATAC_GLD_MSR_CAP) 00000000_002470xxh Page 248 51300001h R/W GeodeLink Device Master Configuration MSR (ATAC_GLD_MSR_CONFIG) 00000000_0000F000h Page 249 51300002h R/W GeodeLink Device SMI MSR (ATAC_GLD_MSR_SMI) 00000000_00000000h Page 250 51300003h R/W GeodeLink Device Error MSR (ATAC_GLD_MSR_ERROR) 00000000_00000100h Page 251 51300004h R/W GeodeLink Device Power Management MSR (ATAC_GLD_MSR_PM) 00000000_00000000h Page 252 51300005h R/W GeodeLink Device Diagnostic MSR (ATAC_GLD_MSR_DIAG) 00000000_00000000h Page 253 Table 5-11. ATAC Specific MSRs Summary MSR Address Type Register Name Reset Value Reference 51300008h R/W I/O Base Address (ATAC_IO_BAR) 00000000_00000001h Page 254 51300009h --- Unused --- --- 51300010h R/W Reset Decode (ATAC_RESET) 00000000_00000000h Page 254 51300011h- 5130001Fh --- Unused --- --- 51300020h R/W Channel 0 Drive 0 PIO (ATAC_CH0D0_PIO) 00000000_00009172h Page 255 51300021h R/W Channel 0 Drive 0 DMA (ATAC_CH0D0_DMA) 00000000_00077771h Page 256 51300022h R/W Channel 0 Drive 1 PIO (ATAC_CH0D1_PIO) 00000000_00009172h Page 258 51300023h R/W Channel 0 Drive 1 DMA (ATAC_CH0D1_DMA) 00000000_00077771h Page 258 51300024h R/W PCI Abort Error (ATAC_PCI_ABRTERR) 00000000_00000000h Page 258 |
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