CS5535 datasheet(46/555 Pages) NSC

46 / 555 page

www.national.com

Revision 0.8

Signal Definitions (Continued)

PWR_BUT#

GPIO28

Power Button. This GPIO can be mapped to the PMC “button-

push” event, that may be used to implement the power ON and the

four-second-delay power OFF functions. Note that GPIO28 comes

up in the AUX_IN mode after reset, enabling this feature.

Any power button change on this input must be at least two

KHZ32_XCI edges (approximately 62 µs) in duration to be cor-

rectly detected. If spurious transitions smaller than this are possi-

ble, then use on-chip GPIO input filter function to insure proper

operation. Additionally, the rise or fall time on this input must be

less than 10 µs. If transition times longer than this are possible,

then use the on-chip GPIO input filter function to insure proper

operation.

From the first power-up of the Standby power domain under which

no filter is enabled, spurious transitions on the first high-to-low

power button push are acceptable as long as the input is eventu-

ally low at least two KHZ32_XCI edges. Additionally, transition

times as slow as one milli-second are acceptable for the first push.

Note that these relaxed requirements work because this input is

effectively a “don’t care” at the hardware level after the first power-

up until software enables use of the power button. Before enabling

use, the software can setup the GPIO filter or other functions as

needed.

Per the discussion of the “skip” feature in Section 4.17 "Power

Management Control" on page 159, this input may be tied to

ground in order for the system to come on immediately when

Standby and Working power are available. Specifically, systems

that do not incorporate a power button should tie this input to

ground.

One side effect of the “skip” feature, is that the platform design

must insure that this input is not low when Standby power is

applied if the “skip” feature is not desired. Specifically, systems

that do incorporate use of a power button must insure that this

input ramps to a “high” no more than 1 µs behind VIO_VSB ramp-

up. Failure to quickly establish a “high” on this input during power-

up could result in a spurious “skip”.

AC_S_IN2

GPIO12

Audio Controller Serial Data Input 2. This input receives serial

data from a second codec. This data stream contains both control

data and ADC audio data. This input data is sampled on the falling

edge of AC_CLK. If the codec’s Ready bit is set in this stream (slot

0, bit 15), then it is functionally OR-ed with AC_SDATA_IN1. Con-

nect to second codec’s serial data output.

SLP_CLK_EN#

GPIO11

Sleep Clock Enable. This signal is a control that is intended to be

connected to the external system clock generator chip. The

intended use is, when high, the clock generator runs; when low,

the clock generator turns off. From reset, a pull-up makes this

GPIO high. The active state of this signal indicates that the

CS5535 is in the Sleep state.

SLEEP_BUT

GPIO13

Sleep Button. This GPIO can be mapped to a PME “button-push”

type event, that may be used to request the system software to put

the system to Sleep.

Table 2-9. GPIOx Available Functions Descriptions (Continued)

Function Name

Ball

No.

GPIO[x]

Type

Description

CS5535 数据表(PDF) 46 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 46 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载