CS5535 datasheet(30/555 Pages) NSC

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Signal Definitions (Continued)

PIN_OPT_LALL

All LPC Pin Option Selection.

0: All LPC pins become GPIOs including LPC_DRQ# and LPC_SERIRQ.

Ball H3 functions as GPIO22

Ball H2 functions as GPIO16

Ball J2 functions as GPIO17

Ball J1 functions as GPIO18

Ball K1 functions as GPIO19

Ball G1 functions as GPIO20

Ball G2 functions as GPIO21

1: All LPC pins are controlled by the LPC controller except LPC_DRQ# and

LPC_SERIRQ use are determined by bits [5:4]. (Default)

Ball H3 functions as LPC_FRAME#

Ball H2 functions as LPC_AD0

Ball J2 functions as LPC_AD1

Ball J1 functions as LPC_AD2

Ball K1 functions as LPC_AD3

When this bit is low, there is an implied high for LPC_DISABLE_IO and

LPC_DISABLE_MEM in MSR_LEG_IO (DD MSR 51400014h).

PIN_OPT_LIRQ

LPC_SERIRQ or GPIO21 Pin Option Selection.

0: Ball G2 is GPIO21.

1: Ball G2 functions as LPC_SERIRQ. (Default)

PIN_OPT_LDRQ

LPC_DRQ# or GPIO20 Pin Option Selection.

0: Ball G1 is GPIO20.

1: Ball G2 functions as LPC_DRQ#. (Default)

3:2

PRI_BOOT_LOC

[1:0]

Primary Boot Location. Determines which chip select asserts for addresses at or

above F0000000h. Except those in the range specified by SEC_BOOT_LOC[1:0].

Defaults to the same value as boot option.

00: LPC ROM.

01: Reserved .

10: Flash.

11: FirmWare Hub.

RSVD

Reserved. Reads return value written. By convention, always write 0. Defaults low.

PIN_OPT_IDE

IDE or Flash Controller Pin Function Selection.

0: All IDE pins associated with Flash Controller. Default if BOS[1:0] = 10.

1: All IDE pins associated with IDE Controller. Default if BOS[1:0] = 00 or 11.

IDE_IRQ0 is multiplexed with GPIO2; therefore, this bit has no affect with regards to

programming IDE_IRQ0.

Table 2-6. DIVIL_BALL_OPT (Continued)

Bit

Name

Description

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