CS5535 datasheet(33/555 Pages) NSC

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Signal Definitions (Continued)

2.2.2

PCI Interface Signals (Note 1)

Signal Name

Ball No.

Type

Description

PCI_CLK

PCI Clock. 33 MHz or 66 MHz.

AD[31:0]

U1, T3, U3,

R4, T4, R5,

T5, U5, T6,

U6, R7, T7,

U7, R8, T8,

U8, R12,

T12, U12,

R13, T13,

U13, R14,

T14, P15,

R15, T15,

P16, T16,

R16, T17,

R17

I/O

PCI Address/Data. AD[31:0] is a physical address during the first

clock of a PCI transaction; it is the data during subsequent clocks.

When the CS5535 is a PCI master, AD[31:0] are outputs during the

address and write data phases, and are inputs during the read data

phase of a transaction.

When the CS5535 is a PCI slave, AD[31:0] are inputs during the

address and write data phases, and are outputs during the read data

phase of a transaction.

C/BE[3:0]#

R6, T9,

U11, U14

I/O

PCI Bus Command and Byte Enables. During the address phase of

a PCI transaction, when FRAME# is active, C/BE[3:0]# define the bus

command. During the data phase of a transaction, C/BE[3:0]# are the

data byte enables.

C/BE[3:0]# are outputs when the CS5535 is a PCI master and inputs

when it is a PCI slave.

PAR

U10

I/O

PCI Parity. PAR is the parity signal driven to maintain even parity

across AD[31:0] and C/BE[3:0]#.

The CS5535 drives PAR one clock after the address phase and one

clock after each completed data phase of write transactions as a PCI

master. It also drives PAR one clock after each completed data phase

of read transactions as a PCI slave.

FRAME#

I/O

PCI Cycle Frame. FRAME# is asserted to indicate the start and dura-

tion of a transaction. It is de-asserted on the final data phase.

FRAME# is an input when the CS5535 is a PCI slave.

Normally connected to a 10k to15k

Ω external pull-up. This signal is

TRI-STATE after reset.

DEVSEL#

R11

I/O

PCI Device Select. DEVSEL# is asserted by a PCI slave, to indicate

to a PCI master and subtractive decoder that it is the target of the cur-

rent transaction.

As an input, DEVSEL# indicates a PCI slave has responded to the

current address.

As an output, DEVSEL# is asserted one cycle after the assertion of

FRAME# and remains asserted to the end of a transaction as the

result of a positive decode. DEVSEL# is asserted four cycles after the

assertion of FRAME# if DEVSEL# has not been asserted by another

PCI device when the CS5535 is programmed to be the subtractive

decode agent.

Normally connected to a 10k to 15k

Ω external pull-up. This signal is

TRI-STATE after reset.

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