CS5535 datasheet(75/555 Pages) NSC

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4.1

GEODELINK INTERFACE UNIT

Many traditional architectures use buses to connect mod-

ules together, usually requiring unique addressing for each

house-keeping be done as new modules are designed and

new devices are created from the module set. Module

select signals can be used to create the unique addresses,

but that can get cumbersome and it requires that the mod-

ule selects be sourced from some centralized location.

To alleviate this issue, National developed an internal bus

architecture called GeodeLink. The GeodeLink architecture

connects the internal modules of a device using the data

channels provided by GeodeLink Interface Units (GLIUs).

Using GLIUs, all internal module port addresses are

derived from the distinct port that the module is connected

to. In this way, a module’s Model Specific Registers (MSRs)

do not have unique addresses until a device is defined.

Also, as defined by the GeodeLink architecture, a module’s

port address depends on the location of the module sourc-

ing the cycle, or source module.

The CS5535 incorporates one GLIU into its device archi-

tecture. Except for the configuration registers that are

required for x86 compatibility, all internal registers are

accessed through a Model Specific Register (MSR) set.

MSRs have a 32-bit address space and a 64-bit data

space. The full 64-bit data space is always read or written

when accessed.

4.1.1

GLIU Port Connections

Table 4-1 shows the GeodeLink Devices connected to each

of the seven GLIU ports on CS5535.

4.1.2

Descriptor Summary

Table 4-2 shows the descriptors reserved for each

GeodeLink Device.

Table 4-1. GLIU Port Connections

Port

Number

Device

GeodeLink PCI South Bridge (GLPCI_SB)

USB Controller #2 (USBC2)

ATA-5 Controller (ATAC)

Diverse Device (DD)

AC97 Audio Controller (ACC)

USB Controller #1 (USBC1)

GeodeLink Control Processor (GLCP)

Table 4-2. GLIU Descriptors Reserved for GeodeLink Devices

Device

Descriptor Type

# of Descriptors

Usage

USBC1

P2D_BMK

Do not hit on keyboard emulation registers.

USBC2

P2D_BMK

Do not hit on keyboard emulation registers.

ATAC

IOD_BM

For IDE master registers.

IOD_BM

Defaults to 1Fxh.

IOD_SC

Defaults to 3F6h.

IOD_BM

COM ports legacy power management.

IOD_BM

For secondary IDE trapping to 17xh.

IOD_SC

For secondary IDE trapping to 376h.

IOD_SC

Keyboard legacy power management.

IOD_SC

LPC ports legacy power management.

IOD_SC

Floppy legacy power management.

ACC

P2D_BM

For memory space registers.

IOD_BM

For I/O space registers.

GLPCI_SB

P2D_BM

For master requests to GX2 GLPCI.

Spares

IOD_BM

Provides the possibility to virtualize NAND Flash

accesses when the IDE/Flash shared pins are in the ‘IDE

Position’. For the ‘Flash Position’, already dedicated IDE

descriptors can be used to virtualize.

IOD_BM

IOD_SC

P2D_BM

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