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CS5535 数据表(PDF) 53 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 53 Page - National Semiconductor (TI) |
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53 / 555 page  Revision 0.8 53 www.national.com Global Concepts and Features (Continued) In addition to the “positive” address decode above, each GLIU has a subtractive port that takes all addresses not assigned to a specific port. There is always a default sub- tractive port path to the boot ROM to allow the central pro- cessor to start executing code from time zero. Thus, from system reset, there is a default memory address path that allows the first processor instruction fetch to: 1) Proceed down through the two GX2 GLIUs; 2) cross the PCI bus to the CS5535; 3) proceed down through the CS5535 GLIU to the default port connected to the DD; and 4) access the boot device connected to the DD. 3.1.7 Special Cycles and BIZZARO Flag The BIZZARO flag is used to indicate special cycles and exceptions to normal packet operation. All special cycles traverse the GLIU system as I/O packets with the BIZZARO flag set. The special cycles are: 1) Interrupt Acknowledge: I/O read from address zero. 2) Shutdown: I/O write to address zero. 3) Halt: I/O write to address one. 3.2 CS5535 MSR ADDRESSING An MSR address consists of the fields shown in Table 3-1. When a GLIU receives an MSR packet, it routes the packet to the port specified in Field 0 but shifts address bits [31:14] to the left by three bits and replaces bits [16:14] with zero. Thus, Field 1 is moved to Field 0, Field 2 is moved to Field 1, etc. The address field always remains unchanged and selects one 64-bit MSR per address value, that is, the address value 0 accesses one 64-bit register, the address value 1 accesses one 64-bit register, the address value 2 accesses one 64-bit register, etc. There are no MSR byte enables. All 64 bits are always written and read. Many CS5535 MSRs are only 32 bits in physical size. In these cases, interface logic discards the upper 32 bits on writes and pads the upper 32 bits on reads. Read padding is undefined. Lastly, CS5535 GLDs only decode enough bits of the address to select one of N MSRs, where N is the total number of MSRs in the device. For example, if a GLD has only 16 MSRs, then the addresses 0x2001, 0x0201, 0x0021, and 0x0x0001 all access MSR number 1, while the addresses 0x200F, 0x020F, 0x002F, and 0x0x000F all access MSR number 15. To access a given GLD, use Table 3-2 "CS5535 MSR Addresses from GX2 Processor" on page 54. Note the tar- get device addresses: GLPCI_SB 5100xxxxh GLIU 5101xxxxh USBC2 5120xxxxh ATAC 5130xxxxh DD 5140xxxxh ACC 5150xxxxh USBC1 5160xxxxh GLCP 5170xxxxh The xxxx portion refers to the MSR addresses as they appear any place within Section 5.0 "Register Descrip- tions" on page 184. To form a complete MSR address, “OR” an address provided in a register description section with the appropriate address above. Table 3-1. MSR Routing Conventions Routing Field 0 Routing Field 1 Routing Field 2 Routing Field 3 Routing Field 4 Routing Field 5 Address Field Bits [31:29] Bits [28:26] Bits [25:23] Bits [22:20] Bits [19:17] Bits [16:14] Bits [13:0] |
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