CS5535 datasheet(89/555 Pages) NSC

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ACC Functional Description (Continued)

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Pausing the bus master can be accomplished by set-

ting the Bus Master Pause bit in its control register.

The bus master stops immediately on the current sam-

ple being processed. Upon resuming, the bus master

(clearing the Bus Master Pause bit), resumes on the

exact sample where it left off.

The bus master can be stopped in the middle of a

transfer by clearing the Bus Master Enable bit in its

control register. In this case, the bus master will not

remember what sample it left off on. If it is re-enabled,

it will begin by reading the PRD entry pointed to by its

PRD Table Address register. If software does not re-

initialize this pointer, it will be pointing to the PRD entry

immediately following the PRD entry that was being

processed. This may be an invalid condition if the bus

master was disabled while processing the last PRD in

a PRD table (PRD Table Address register pointing to

memory beyond the table).

Note that if the Bus Master Error bit is set, the interrupt

service routine should refill two buffers instead of one,

because a previous interrupt was missed (unless it

was intentionally missed). For this to work correctly,

the service routine should read the Second Level

Audio IRQ Status register, fill the buffer of the bus

master needing service, read the bus master’s IRQ

Status register, and then fill the next buffer if the Bus

Master Error bit was set. Failing to fill the first buffer

before reading the IRQ Status register would possibly

resume the bus master too early and result in sound

being played twice or data being overwritten (if record-

ing).

Codec Register Access

The ACC provides a set of registers that serve as an inter-

face to the AC97 codec’s registers. The Codec Command

codec register. The Codec Status register allows software

to read back the data from the codec after a read operation

has completed. Since the AC Link runs very slow relative to

core CPU speed (and therefore software speed), it is nec-

essary for software to wait between issuing commands to

the codec.

For register reads, software specifies a command address

and sets both the read/write flag and the Codec Command

New flag in the Codec Control register. Software must then

wait for the Codec Status New bit to be set before using the

returned status data in the Codec Status register. Before

issuing another read command, software must wait for the

Codec Command New flag to be cleared by hardware.

(Note: Codec Command New will clear before Codec Sta-

tus New is set; therefore, a second read can be issued

before the result of the current read is returned).

For register writes, software specifies a command address

and command data using the Codec Control register. At

the same time it must set the Codec Command New flag.

Before issuing another read or write, software must wait for

the Codec Command New flag to clear.

See Section 5.3 "AC97 Audio Codec Controller Register

Descriptions" for details on the Codec register interface.

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