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CS5535 数据表(PDF) 83 Page - National Semiconductor (TI) |
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CS5535 数据表(HTML) 83 Page - National Semiconductor (TI) |
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83 / 555 page ![]() ACC Functional Description (Continued) www.national.com 83 Revision 0.8 4.3.4 Codec Interface 4.3.4.1 AC Link Serial Interface Protocol The following figures outline the slot definitions and timing scheme of the AC Link serial protocol. Figure 4-4. AC Link Slot Scheme Figure 4-5. AC Link Output Frame Figure 4-6. AC Link Input Frame TAG CMD PCM PCM LINE1 PCM PCM PCM PCM RSVD HSET GPIO AC_S_SYNC AC_S_OUT (Outgoing Stream) AC_S_IN Data Phase TAG ADDR CMD DATA LEFT RIGHT DAC CEN L SUR R SUR LFE DAC CNTL TAG STATUS PCM PCM LINE1 MIC RSVD HSET GPIO ADDR STATUS DATA LEFT RIGHT ADC ADC ACD STATUS or AC_S_IN2 (Incoming Stream) RSVD RSVD RSVD 01234 5 6789 10 11 12 Slot # Phase Valid Frame Slot 1 Slot 2 Slot 12 End of AC_CLK AC_S_SYNC Time slot “valid” bits (“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 Tag Phase Data Phase 48 kHz (20.8 µs) 12.288 MHz (81.4 ns) AC_S_OUT “0” “0” “0” 19 0 19 19 019 00 Slot 3 Previous Frame Codec Ready Slot 1 Slot 2 Slot 12 End of Time slot “valid” bits (“1” = Time slot contains valid PCM data) Slot 1 Slot 2 Slot 3 Slot 12 AC_S_IN or AC_S_IN2 “0” “0” “0” “19” 0 19 0 19 0 19 0 AC_CLK AC_S_SYNC Tag Phase Data Phase 48 kHz (20.8 µs) 12.288 MHz (81.4 ns) Previous Frame |
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