CS5535 datasheet(69/555 Pages) NSC

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Global Concepts and Features (Continued)

VSA sets EN[n] high. This action sets ASMI[n+1] high

again and causes another CS5535 ASMI.

VSA begins to return to the process interrupted by the

original ASMI, but notes SMI into the processor is still

asserted and returns to step 3.

10) If there was no Event[Y] at any point above, return to

the interrupted process.

Note:

Step 5 above could occur at any time between step

2 and step 9, or the Event[Y] could come after step

10. Regardless, the same VSA approach is used in

order not to miss any events.

3.8.3.2

Apparent SSMI

An SSMI event is associated with an I/O space access to a

specific address or range of addresses. If SSMIs are

enabled for the given address, then the hardware traps or

blocks access to the target register. The actual register

write and/or read operation is not performed. Generally,

only write operations are trapped, but there are cases of

trapping writes and reads. The CS5535 does not support

SSMIs, however, the CS5535 supports a mechanism

called “Apparent SSMI” using ASMIs. (Hereafter “Apparent

SSMI” is referred to as “SSMI”.)

The CS5535 insures that the ASMI is taken on the I/O

instruction boundary. The ASMI reaches the CPU before a

target ready is signaled on the PCI bus. This action creates

an SSMI because the I/O instruction will not complete

before ASMI reaches the CPU. VSA software then exam-

ines the GLPCI_SB GLD_SMI_MSR to determine if an

SSMI has occurred from an I/O trap.

Figure 3-8. In-Direct ASMI Behavioral Model

Native Event

FLAG Bit[x]

Clear_By_Software

Set_By_Software

Clear_By_Software

Event

[X]

Bit[m]

Other

FLAG Bits

SMI MSR

FLAG Bit[n+1]

ASMI

[n+1]

GLD ASMI

Clear_By_Software

Set_By_Software

Clear_By_Software

Bit[n]

Other ASMI

FLAG Bits

Native Event

Summary Signal

(NESS)

Event

[X]

ALL

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