CS5535 datasheet(59/555 Pages) NSC

59 / 555 page

Revision 0.8

www.national.com

Global Concepts and Features (Continued)

RESET_OUT# is de-asserted synchronous with the low-to-

high edge of PCI_CLK. The de-assertion is delayed from

internal_reset using a counter in the Power Management

Controller. This counter is driven by the 32 kHz clock and is

located in the Standby power domain. The value of the

counter is programmable but defaults to 0x0_0100 (256

edges). 31.25 µs per edge times 256 equals an 8 ms delay.

Note

this

counter

default

established

RESET_STAND# and is not effected by RESET_WORK#.

Therefore, the delay value may be changed and then the

system can be reset with the new value.

Note the special consideration for TAP Controller reset.

When boundary scan is being performed, internal compo-

nent operation is not possible due to the scanning signals

on the I/Os. Under this condition, it is desirable to hold the

component internals in reset while the boundary scan is

being performed by the TAP Controller. However, under

normal operation, it is desirable to reset the TAP Controller

with the other logic in the Working domain during power

management sequences.

Achieving these dual goals is accomplished as follows:

For boundary scan:

• Assert RESET_STAND#, causing internal

power_good_standby to go low. This causes the

complete component to reset, except for the TAP

Controller. Keep this input held low throughout boundary

scan operations.

• Assert and de-assert RESET_WORK# as needed to

reset the TAP Controller.

For normal operation:

• The internal Power Good Standby will be high, meaning

the TAP Controller reset asserts any time the Standby

state is active or anytime RESET_WORK# is active.

Figure 3-6. Reset Logic

Faulted

Event

Capture

Power

Manage

Standby

State

Controller

Faulted

Event

Status

& immediately

enter Standby

state

unconditionally

Fail-safe Power Off Alarm

Thermal Alarm

Low Power Alarm

Shutdown Special Cycle

MFGPT WATCHDOG

DD Bad Packet

GLCP Soft Reset

DD Soft Reset

Working Power Fail

RESET_WORK#

Normal Software Request for Standby State

working

work_aux

standby_state

32kHZ_CLK

De-assert

Delay

PCI_CLK

RESET_OUT#

LVD

(Low

Voltage

Detect)

VCORE

VCORE_VSB

VIO_VSB

RESET_STAND#

ATA

Controller

IDE_RESET#

Internal Reset

to all Working

Domain Logic

except TAP

Controller

Power Good Working

Power Good Standby

(Standby Domain Reset When Low)

TAP Controller Reset

standby_state

CS5535 数据表(PDF) 59 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 59 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5535 数据表(PDF) 59 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 59 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载