CS5535 datasheet(35/555 Pages) NSC

35 / 555 page

Revision 0.8

www.national.com

Signal Definitions (Continued)

2.2.3

IDE/Flash Interface Signals

The IDE and Flash interface signals are multiplexed together on the same balls as shown in Table 2-7. Section 2.2.3.1 pro-

vides the names and functions of these signals when the interface is in the IDE mode and Section 2.2.3.2 when in Flash

mode (NOR Flash/GPCS and NAND Flash modes).

Table 2-7. IDE and Flash Ball Multiplexing

Ball No.

IDE Mode

NOR Flash/GPCS Mode

NAND Flash Mode

Address Phase

Data Phase

B11, A12

IDE_AD[2:1]

FLASH_AD[27:26]

FLASH_AD[2:1]

---

A11

IDE_AD0

FLASH_AD25

FLASH_AD0

FLASH_CLE

B15, B16, A17, C17,

D16, D17, E17

IDE_DATA[14:8]

FLASH_AD[24:18]

FLASH_AD[9:3]

---

E16, E15, D15, B17,

C16, C15, A15, B14

IDE_DATA[7:0]

FLASH_AD[17:10]

FLASH_IO[7:0]

C14

IDE_DATA15

FLASH_ALE

B10

IDE_CS0#

FLASH_CS0#

FLASH_CE0#

C10

IDE_CS1#

FLASH_CS1#

FLASH_CE1#

B13

IDE_IOR0#

FLASH_RE#

C13

IDE_IOW0#

FLASH_WE#

A14 (Note 1)

Note 1.

Ball A14 is the only ball that changes direction from IDE to Flash (input when in IDE mode, output when in Flash

mode). If this interface is to be switched between IDE and Flash modes, then ball A14 needs an external pull-up to

keep it high during IDE mode.

IDE_DREQ0

FLASH_CS2#

FLASH_CE2#

C12

IDE_DACK0#

FLASH_CS3# (Boot Flash Chip Select)

FLASH_CE3#

A13

IDE_RDY0

FLASH_IOCHRDY

FLASH_RDY/BUSY#

2.2.3.1

IDE Interface Signals

Signal Name

Ball No.

Type

Description

IDE_IRQ0

B12

IDE Interrupt Request Channel 0. This signal is required for all IDE

applications that use IDE DMA modes. It is available on GPIO2, which

must be configured in the AUX_IN mode. If an IDE application will not

use IDE DMA modes, or if the Flash interface will be used instead of

the IDE interface, then this signal may be used as GPIO2.

IDE_RESET#

F15

IDE Reset. An internal reset that is the functional “OR” of inputs

RESET_WORK# and RESET_STAND#. It may also be controlled

directly via an MSR (see Section 5.4.2.2 "Reset Decode

(ATAC_RESET)" on page 254). This signal resets all the devices that

are attached to the IDE interface.

IDE_AD[2:0]

B11, A12,

A11

IDE Address Bits. These address bits are used to access a register

or data port in a device on the IDE bus.

IDE_DATA[15:0]

C14, B15,

B16, A17,

C17, D16,

D17, E17,

E16, E15,

D15, B17,

C16, C15,

A15, B14

I/O

IDE Data Lines. IDE_DATA[15:0] transfers data to/from the IDE

devices.

CS5535 数据表(PDF) 35 Page - National Semiconductor (TI)

CS5535 数据表(HTML) 35 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载