CS5535 datasheet(98/555 Pages) NSC

98 / 555 page

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Revision 0.8

DIVIL Functional Description (Continued)

4.6.1.2

Variable Target Size I/O LBARs

This discussion applies to the following LBARs:

• MSR 51400010h: Flash Chip Select 0

(MSR_LBAR_FLSH0) with bit 34 = 0 (I/O mapped)

• MSR 51400011h: Flash Chip Select 1

(MSR_LBAR_FLSH1) with bit 34 = 0 (I/O mapped)

• MSR 51400012h: Flash Chip Select 2

(MSR_LBAR_FLSH2) with bit 34 = 0 (I/O mapped)

• MSR 51400013h: Flash Chip Select 3

(MSR_LBAR_FLSH3) with bit 34 = 0 (I/O mapped)

Note:

Flash Chip Selects [3:0] can be programmed for

I/O or a memory space. See Section 4.6.1.3

"Memory LBARs".

The I/O LBAR works just like the Fixed style, except the

size of the IO_MASK has been expanded to cover the

entire address range (see Figure 4-12). In the Fixed style,

the IO_MASK applies to bits [15:12] but for Variable style,

the IO_MASK applies to bits [15:4]. If all bits are set, then

the target size is 16 bytes and base address bits [15:4]

determine the base. Base bits [3:0] are a “don't care” and

are effectively forced to zero by the hardware. Thus, the

smallest I/O target is 16 bytes. As the LSBs of IO_MASK

are cleared, the “target space” expands. For example,

assume a 64-byte device is desired in I/O space. The

IO_MASK = FFCh, base address bits [15:6] are pro-

grammed to the desired base, and base address bits [5:4]

are cleared (see Rule on page 97).

4.6.1.3

Memory LBARs

This discussion applies to the following LBARs:

• MSR 51400009h: KEL from USB Host Controller 1

(MSR_LBAR_KEL1)

• MSR 51400010h: Flash Chip Select 0

(MSR_LBAR_FLSH0) with bit 34 = 1 (memory mapped)

• MSR 51400011h: Flash Chip Select 1

(MSR_LBAR_FLSH1) with bit 34 = 1 (memory mapped)

• MSR 51400012h: Flash Chip Select 2

(MSR_LBAR_FLSH2) with bit 34 = 1 (memory mapped)

• MSR 51400013h: Flash Chip Select 3

(MSR_LBAR_FLSH3) with bit 34 = 1 (memory mapped)

• MSR 5140000Ah: KEL from USB Host Controller 2

(MSR_LBAR_KEL2)

Note:

The Flash Chip Selects [3:0] can be programmed

for an I/O space or a Memory space.

For memory space, the LBAR works exactly like the Vari-

able style (see Figure 4-13), except that clearing the LSBs

of the MEM_MASK begins to make sense. For example,

assume there is a 64 kB external ROM that is going to be

connected to Flash Chip Select 0. Such a device needs

address bits [15:0]. The MEM_MASK would normally be

programmed to FFFF0h and base address bits [31:16]

would be programmed to the desired base. The values in

base address [15:12] would be cleared because the asso-

ciated mask bits are cleared (see Rule on page 97). Lastly,

the memory target can not be smaller than 4 kB.

Figure 4-12. I/O Space LBAR - Variable Target Size

Figure 4-13. Memory Space LBAR

ADDR[15:4]

I/O_MASK

Compare

BASE_ADDR

Hit

[15:4]

ADDR[31:12]

MEM_MASK

Compare

BASE_ADDR

Hit

[31:12]

Note:

The memory mask is always 20 bits, which is equal to the number of memory base address bits.

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