CS5535 datasheet(13/555 Pages) NSC

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Architecture Overview (Continued)

1.1

GEODELINK PCI SOUTH BRIDGE

The GeodeLink PCI South Bridge (GLPCI_SB) provides a

PCI interface for the CS5535. It acts as a PCI master or

slave in providing PCI transactions to and from the CS5535

and the PCI bus. A special serial interface to the GX2 pro-

cessor, the CPU Interface Serial (CIS), is provided that

assists in the transfer of information between the CS5535

and the GX2.

The interface is complaint to PCI specification v2.2 and

may operate at up to 66 MHz. Optional bus signals PERR#,

SERR#, LOCK#, and CLKRUN are not implemented.

Within a PCI burst, zero wait state operation is achieved.

The PCI interface supports programmable IDSEL selec-

tion, and can handle inbound transactions immediately

after system reset.

1.2

GEODELINK CONTROL PROCESSOR

The GeodeLink Control Processor is responsible for debug

support and monitors system clocks in support of PMC

operations.

The GLCP interfaces with a JTAG compatible Test Access

Port (TAP) Controller that is IEEE 1149.1 compliant. During

debug, it can be used to pass GeodeLink packets to/from

the GLIU. It is also used to support manufacturing test.

1.3

ATA-5 CONTROLLER

The CS5535 integrates a fully-buffered, ATA-5 compliant

(UDMA/66) IDE interface. The IDE interface supports one

channel, which in turn supports two devices that can oper-

ate in PIO modes 1 to 4, MDMA modes 0 to 2, or UDMA/66

modes 0 to 4.

This interface is shared with the Flash interface, using the

same balls. The interface usage, immediately after reset, is

defined by the boot options selected (see Table 2-5 "Boot

Options Selection" on page 29). After reset, the interface

may be dynamically altered using the Ball Options MSR

(see Table 2-6 "DIVIL_BALL_OPT" on page 29).

The IDE interface provides a variety of features to optimize

system performance, including 32-bit disk access, post

write buffers, bus master, MDMA, look-ahead read buffer,

and prefetch mechanism.

The IDE interface timing is completely programmable. Tim-

ing control covers the command active and recover pulse

widths, and command block register accesses. The IDE

data transfer speed for each device on each channel can

be independently programmed allowing high-speed IDE

peripherals to coexist on the same channel as older, com-

patible devices.

The CS5535 also provides a software accessible buffered

reset signal to the IDE drive. The IDE_RST# signal is

driven low during reset to the CS5535 and can be driven

low or high as needed for device-power-off conditions.

1.4

UNIVERSAL SERIAL BUS CONTROLLERS

The CS5535 provides four USB ports, controlled by two

independent controllers (USBC1 and USBC2) for 2x

enhanced system performance. There are two ports asso-

ciated with each controller for a total of four. Separate

power and ground pins for the transceivers are provided to

accommodate various system designs and provide supe-

rior noise immunity. Each pair of ports has an associated

power control line, and there is a common over-current

sense line for all four ports, compatible with National’s

LM3526 dual-port USB power switch. The controllers are

OpenHost Controller Interface (OHCI) v1.0 compliant, and

the ports adhere to the USB v1.1 specification, with exter-

nal crimp protection diodes.

1.5

AUDIO CODEC 97 (AC97) CONTROLLER

The audio subsection of the CS5535 consists of three 32-

bit stereo-buffered bus masters (two for output, one for

input) and five 16-bit mono-buffered bus masters (three for

output, two for input), whose function is to transport audio

data between system memory and external AC97 codecs.

This arrangement is capable of producing multi-channel

5.1 surround sound (left, center, right, left rear, right rear,

and low frequency effects).

The codec interface is AC97 v2.1 compliant and contains

Serial In (x2), Serial Out, Sync Out, and Bit Clock allowing

support for any AC97 codec with Sample Rate Conversion

(SRC). Additionally, the interface supports the industry-

standard 16-bit pulse code modulated (PCM) format.

1.6

DIVERSE DEVICE

A suite of 82xx devices provide all the legacy PC function-

ality required by most designs, including two PICs (pro-

grammable interrupt controllers), one PIT (programmable

interval timer) with three channels, and DMA (direct mem-

ory

access)

functions.

The

CS5535

contains

eight

MFGPTs (multi-function general purpose timers) that can

be used for a variety of functions. A number of GPIOs (gen-

eral-purpose input/outputs) are provided, and are assigned

to system functions on power-up (i.e., LPC port); each of

these may be reassigned and given different I/O character-

istics such as debounce, edge-triggering, and so forth.

The Diverse Integration Logic (DIVIL) holds the devices

together and provides overall control and management via

MSRs.

1.6.1

Legacy DMA

The CS5535 DMA controller consists of two cascaded

8237A-type DMA controllers that together support four 8-

bit channels. The DMA controller is used to provide high

speed transfers between internal chip sources. It has full

32-bit address range support via high-page registers. An

internal mapper allows routing of any of seven internal

DMA sources to the four 8-bit DMA channels.

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