LPC2917 datasheet(40/68 Pages) PHILIPS

40 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

40 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

8.7.7.2

Description

See section Section 8.4.3.2 for a description of the timers.

8.7.7.3

MSCSS timer-pin description

MSCSS timer 0 has no external pins.

MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined

with other functions on the port pins of the LPC2917/19. Table 22 shows the MSCSS

timer 1 external pin.

8.7.7.4

MSCSS timer-clock description

The Timer modules in the MSCSS are clocked by CLK_MSCSS_MTMRx (x = 0-1), see

Section 7.2.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for

power management. The frequency of all these clocks is identical to CLK_MSCSS_VPB

since they are derived from the same base clock BASE_MSCSS_CLK.

Note that, unlike the timer modules in the Peripheral SubSystem, the actual timer counter

registers run at the same clock as the VPB system interface CLK_MSCSS_VPB. This

clock is independent of the AHB system clock.

If a timer module is not used its CLK_MSCSS_MTMRx branch clock can be switched off.

8.8 Power, clock and reset control subsystem

8.8.1 Overview

The Power, Clock and Reset Control Subsystem (PCRSS) in the LPC2917/19 includes a

Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management

Unit (PMU).

8.8.2 Description

Figure 11 provides an overview of the PCRSS. An AHB-to-DTL bridge takes care of

communication with the AHB system bus.

Table 22.

MSCSS timer 1 pin

Symbol

Direction

Description

MSCSS PAUSE

pause pin for MSCSS timer 1

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