LPC2917 datasheet(5/68 Pages) PHILIPS

5 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

5 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

Block diagram

Fig 1.

LPC2917/19 block diagram

IEEE 1149.1 JTAG TEST and

DEBUG INTERFACE

LPC2917/19

DTCM

16 Kb

ITCM

16 Kb

ARM968E-S

Multi-layer AHB

system bus

m = master port

s = slave port

External Static Memory

Controller (SMC)

Embedded

SRAM Memory 32 Kb

SRAM Controller #0

Embedded

FLASH Memory

512/768 Kb

FLASH Memory Controller (FMC)

Embedded

SRAM Memory 16 Kb

SRAM Controller #1

GLOBAL ACCEPTANCE

FILTER

2 Kbyte Static RAM

LIN MASTER 0/1

CAN Controller

0, 1

Vectored Interrupt

Controller (VIC)

Modulation and Sampling

Control Subsystem

PWM 0, 1, 2, 3

ADC 1, 2

Timer 0, 1 (MTMR)

Power Clock Reset

Control Subsystem

Power Management Unit (PMU)

Reset Generation Unit (RGU)

Clock Generation Unit (CGU)

General Subsystem

Event Router (ER)

System Control Unit (SCU)

Chip Feature ID (CFID)

Peripheral Subsystem

General Purpose IO (GPIO)

0, 1, 2, 3

Timer (TMR)

0, 1, 2, 3

Watchdog Timer (WDT)

UART 0, 1

SPI 0, 1, 2

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