LPC2917 datasheet(24/68 Pages) PHILIPS

24 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

24 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

• CLK_SAFE see Section 7.2.2

8.4.2 Watchdog timer

8.4.2.1

Overview

The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable

amount of time if the processor enters an error state. The watchdog generates a system

reset if the user program fails to trigger it correctly within a predetermined amount of time.

Key features:

• Internal chip reset if not periodically triggered

• Timer counter register runs on always-on safe clock

• Optional interrupt generation on watchdog timeout

• Debug mode with disabling of reset

• Watchdog control register change-protected with key

• Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.

8.4.2.2

Description

The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.

The watchdog should be programmed with a time-out value and then periodically

restarted. When the watchdog times out it generates a reset through the RGU.

To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled

via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing

to the clear-interrupt register.

Another way to prevent resets during debug mode is via the Pause feature of the

Watchdog Timer. The watchdog is stalled when the ARM9 is in debug mode and the

PAUSE_ENABLE bit in the Watchdog Timer Control register is set.

The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains

a reset source register to identify the reset source when the device has gone through a

reset. See Section 8.8.5.

8.4.2.3

Pin description

The watchdog has no external pins.

8.4.2.4

Watchdog timer clock description

The Watchdog Timer is clocked by two different clocks; CLK_SYS_PESS and

CLK_SAFE, see Section 7.2.2. The register interface towards the system bus is clocked

by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which

is always on.

8.4.3 Timer

8.4.3.1

Overview

The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in

the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral

base addresses. This section describes the four timers in the peripheral subsystem. Each

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