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LPC2917 数据表(PDF) 28 Page - NXP Semiconductors |
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LPC2917 数据表(HTML) 28 Page - NXP Semiconductors |
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28 / 68 page ![]() LPC2917_19_1 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 — 15 November 2007 28 of 68 NXP Semiconductors LPC2917/19 ARM9 microcontroller with CAN and LIN Depending on the operating mode selected, the SPI_CS_OUT outputs operate as an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format or an active-LOW chip select for SPI. Each data frame is between four and 16 bits long, depending on the size of words programmed, and is transmitted starting with the MSB. There are two basic frame types that can be selected: • Texas Instruments synchronous serial • Motorola Serial Peripheral Interface 8.4.5.3 Modes of operation The SPI module can operate in: • Master mode: – Normal transmission mode – Sequential slave mode • Slave mode 8.4.5.4 SPI pin description The three SPI modules in the LPC2917/19 have the pins listed below. The pins are combined with other functions on the port pins of the LPC2917/19, see Section 8.3.3. Table 16 shows the SPI pins (x runs from 0 to 2; y runs from 0 to 3). [1] Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. [2] In slave mode there is only one chip-select input pin, SPIx SCS0. The other chip selects have no function in slave mode. 8.4.5.5 SPI clock description The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx (x = 0-2), see Section 7.2.2. Note that each SPI has its own CLK_SPIx branch clock for power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx. The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on the interface. Table 16. SPI pins Symbol Direction Description SPIx SCSy in/out SPIx chip select[1][2] SPIx SCK in/out SPIx clock[1] SPIx SDI in SPIx data input SPIx SDO out SPIx data output |
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