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LPC2917 数据表(PDF) 56 Page - NXP Semiconductors |
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LPC2917 数据表(HTML) 56 Page - NXP Semiconductors |
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56 / 68 page ![]() LPC2917_19_1 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 1.01 — 15 November 2007 56 of 68 NXP Semiconductors LPC2917/19 ARM9 microcontroller with CAN and LIN Internal clock fclk(sys) System clock frequency. See Table 23. 10 - 80 MHz Tclk(sys) System clock period. See Table 23. 12.5 - 100 ns Low-Power Ring Oscillator fref(RO) RO reference frequency. 0.36 0.4 0.42 MHz tstartup Start-up time. At maximum frequency [2]. -6 100 μs Oscillator fi(osc) Oscillator input frequency. Maximum frequency is the clock input of an external clock source applied to the Xin pin. 10 - 80 MHz tstartup Start-up time. At maximum frequency. [2] [3] - 500 - μs PLL fi(PLL) PLL input frequency. 10 - 25 MHz fo(PLL) PLL output frequency. 10 - 160 MHz CCO; direct mode. 156 - 320 MHz Analog-to-digital converter fi(ADC) ADC input frequency. [4] 4- 4.5 MHz fs(max) Maximum sampling rate. fi(ADC) = 4.5 MHz; fs =fi(ADC)/(n+1) with n=resolution resolution 2 bit - - 1500 ksample/s resolution 10 bit - - 400 ksample/s tconv Conversion time. In number of ADC clock cycles. 3 - 11 cycles In number of bits. 2 - 10 bits Flash memory tinit Initialization time. - - 150 μs twr(pg) Page write time. 0.95 1 1.05 ms ter(sect) Sector erase time. 95 100 105 ms tfl(BIST) Flash word BIST time. - 38 70 ns tacc(clk) clock access time - - 63.4 ns tacc(addr) address access time - - 60.3 ns external static memory controller ta(R)int Internal read-access time. - - 20.5 ns Table 31. Dynamic characteristics …continued VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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