LPC2917 datasheet(46/68 Pages) PHILIPS

46 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

46 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

Triple output phases

For applications that require multiple clock phases two additional clock outputs can be

enabled by setting register P23EN to ’1’, thus giving three clocks with a 120

° phase

difference. In this mode all three clocks generated by the analog section are sent to the

output dividers. When the PLL has not yet achieved lock the second and third phase

output dividers run unsynchronized, which means that the phase relation of the output

clocks is unknown. When the PLL LOCK register is set the second and third phase of the

output dividers are synchronized to the main output clock CLKOUT PLL, thus giving three

clocks with a 120

° phase difference.

Direct output mode

In normal operating mode (with DIRECT set to ’0’) the CCO clock is divided by 2, 4, 8 or

16 depending on the value on the PSEL[1:0] input, giving an output clock with a 50% duty

cycle. If a higher output frequency is needed the CCO clock can be sent directly to the

output by setting DIRECT to ’1’. Since the CCO does not directly generate a 50% duty

cycle clock, the output clock duty cycle in this mode can deviate from 50%.

Power-down control

A power-down mode has been incorporated to reduce power consumption when the PLL

clock is not needed. This is enabled by setting the PD control register bit. In this mode the

analog section of the PLL is turned off, the oscillator and the phase-frequency detector are

stopped and the dividers enter a reset state. While in power-down mode the LOCK output

is low, indicating that the PLL is not in lock. When power-down mode is terminated by

clearing the PD control-register bit the PLL resumes normal operation, and makes the

LOCK signal high once it has regained lock on the input clock.

8.8.4.4

CGU pin description

The CGU module in the LPC2917/19 has the pins listed in Table 24 below.

Fig 14. PLL block diagram

P23

CCO

/ MDIV

clkout120 /

clkout240

/ 2PDIV

MSEL

PSEL

P23EN

Input clock

Bypass

Direct

clkout

Table 24.

CGU pins

Symbol

Direction

Description

XOUT_OSC

out

Oscillator crystal output

XIN_OSC

Oscillator crystal input or external clock input

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