LPC2917 datasheet(55/68 Pages) PHILIPS

55 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

55 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

[1]

All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at Tamb = 125 °C on wafer

level. Cased products are tested at Tamb =25 °C (final testing). Both pre-testing and final testing use correlated test conditions to cover

the specified temperature and power-supply voltage range.

[2]

Leakage current is exponential to temperature; worst-case value is at 125 C Tvj. All clocks off. Analog modules and FLASH powered

down.

[3]

For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input

capacitance to ADC.

[4]

This value is the minimum drive capability. Maximum short-circuit output current is 33 mA (drive HIGH-level, shorted to ground) or

−38 mA. (drive LOW-level, shorted to V

DD(IO)). The device will be damaged if multiple outputs are shorted.

[5]

Cxtal is crystal load capacitance and Cext are the two external load capacitors.

[6]

The power-up reset has a time filter: VDD(CORE) must be above Vtrip(high) for 2 μs before reset is de-asserted; VDD(CORE) must be below

Vtrip(low) for 11 μs before internal reset is asserted.

[7]

Not 5 V-tolerant when pull-up is on.

[8]

For I/O Port 0, the maximum input voltage is defined by VI(ADC).

[9]

This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are

based on simulation results.

12. Dynamic characteristics

Oscillator

Rs(xtal)

Crystal series resistance.

fosc = 10 MHz to 15 MHz

[5]

Cxtal =10pF;

Cext =18pF

160

Cxtal =20pF;

Cext =39pF

fosc = 15 MHz to 20 MHz

[5]

Cxtal =10pF;

Cext =18pF

Input capacitance of

XIN_OSC.

[9] -2

Power-up reset

Vtrip(high)

High trip-level voltage.

[6] 1.2

1.4

1.6

Vtrip(low)

Low trip-level voltage.

[6] 1.1

1.3

1.5

Vtrip(dif)

Difference between high

and low trip-level

voltages.

[6] 50

120

180

Table 30.

Static characteristics …continued

VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj =-40 °Cto+125 °C; all voltages are

measured with respect to ground; positive currents flow into the IC; unless otherwise specified.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 31.

Dynamic characteristics

VDD(CORE) =VDD(OSC_PLL) ; VDD(IO) = 2.7 V to 3.6 V; VDD(A3V3) = 3.0 V to 3.6 V; Tvj = −40 °C; all voltages are measured with

respect to ground; positive currents flow into the IC; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

I/O pins

tTHL

HIGH-to-LOW

transition time.

CL = 30 pF

13.8

tTLH

LOW-to-HIGH

transition time.

CL = 30 pF

13.8

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