LPC2917 datasheet(14/68 Pages) PHILIPS

14 / 68 page

LPC2917_19_1

Preliminary data sheet

Rev. 1.01 — 15 November 2007

14 of 68

NXP Semiconductors

LPC2917/19

ARM9 microcontroller with CAN and LIN

[1]

This clock is always on (cannot be switched off for system safety reasons)

[2]

In the peripheral subsystem parts of the Timers, Watchdog Timer, SPI and UART have their own clock

source. See Section 8.4 for details.

[3]

In the Power Clock and Reset Control subsystem parts of the CGU, RGU PMU have their own clock

source. See Section 8.8 for details.

[4]

The clock should remain activated when system wake-up on timer or UART is required.

Block description

8.1 Flash memory controller

8.1.1 Overview

The Flash Memory Controller (FMC) interfaces to the embedded flash memory for two

tasks:

• Providing memory data transfer

• Memory configuration via triggering, programming and erasing

BASE_MSCSS_CLK

CLK_MSCSS_VPB

VPB side of the MSCSS

CLK_MSCSS_MTMR0

Timer 0 in the MSCSS

CLK_MSCSS_MTMR1

Timer 1 in the MSCSS

CLK_MSCSS_PWM0

PWM 0

CLK_MSCSS_PWM1

PWM 0

CLK_MSCSS_PWM2

PWM 0

CLK_MSCSS_PWM3

PWM 0

CLK_MSCSS_ADC1_V

VPB side of ADC 1

CLK_MSCSS_ADC2_V

VPB side of ADC 2

BASE_UART_CLK

CLK_UART0

UART 0 interface clock

CLK_UART1

UART 1 interface clock

BASE_SPI_CLK

CLK_SPI0

SPI 0 interface clock

CLK_SPI1

SPI 1 interface clock

CLK_SPI2

SPI 2 interface clock

BASE_TMR_CLK

CLK_TMR0

Timer 0 clock for counter part

CLK_TMR1

Timer 1 clock for counter part

CLK_TMR2

Timer 2 clock for counter part

CLK_TMR3

Timer 3 clock for counter part

BASE_ADC_CLK

CLK_ADC1

Control of ADC 1, capture sample

result

CLK_ADC2

Control of ADC 2, capture sample

result

BASE_CLK_TESTSHELL

CLK_TESTSHELL_IP

Table 7.

Base clock and branch clock overview …continued

Base clock

Branch clock name

Parts of the device clocked by

this branch clock

Remark

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