ST52F510 datasheet(69/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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11 WATCHDOG TIMER

11.1 Functional Description

The Watchdog Timer (WDT) is used to detect the

occurrence of a software fault, usually generated

by external interference or by unforeseen logical

conditions, which causes the application program

to abandon its normal sequence. The WDT circuit

generates an ICU reset on expiry of a programmed

time period, unless the program refreshes the

WDT before the end of the programmed time

delay. Sixteen different delays can be selected by

using the WDT configuration register.

After the end of the delay programmed by the

configuration register, if the WDT is active, it starts

a reset cycle pulling the reset signal low.

Once the WDT is activated, the application

program has to refresh the counter (by the

WDTRFR instruction) during normal operation in

order to prevent an ICU reset.

In ST52F510/F513/F514 devices it is possible to

choose

between

“Hardware”

“Software”

Watchdog.

The

Hardware

WDT

allows

the

counting to avoid unwanted stops for external

interferences. The first mode is always enabled

unless the Option Byte 4 (WDT_EN) is written with

a special code (10101010b): only this code can

switch the WDT in “Software” Mode, the other 255

possibilities keep the “Hardware” Mode enabled.

The WDT is started and refreshed by using the

WDTRFR instruction. When the software mode is

enabled, the WDTSLP instruction stops the WDT

avoiding timeout resets.

When the WDT is in Hardware Mode, neither the

WDTSLP instruction nor external interference can

stop the counting. The “Hardware” WDT is always

enabled after a Reset.

Figure 11.1 Watchdog Block Diagram

The working frequency of WDT (PRES CLK in the

Figure 11.1) is equal to the clock master. The clock

master is divided by 500, obtaining the WDT CLK

signal that is used to fix the timeout of the WDT.

According to the WDT_CR Configuration Register

values, a WDT delay between 0.1ms and 937.5ms

can be defined when the clock master is 5 MHz. By

changing the clock master frequency the timeout

delay

can

calculated

according

the

configuration register values. The first 4 bits of the

WDT_CR register are used, obtaining 16 different

delays.

11.2 Register Description

SW Watchdog Enable (WDT_EN)

Option Byte 4 (04h)

Reset Value: 0000 0000 (00h)

Bit 7-0: WDTEN7-0 SW Watchdog Enable byte

Writing the code 10101010 in this byte the

Software Watchdog mode is enabled.

Configuration Register

RESET

WDTRFR

PRES CLK = CLK MASTER

WDTSLP

PRESCALER

WDT

RESET

GENERATOR

RESET

W TD CLK

Table 11.1 Watchdog Timing Range (5 MHz)

WDT timeout period (ms)

min

0.1

max

937.5

WDTEN7 WDTEN6 WDTEN5 WDTEN4 WDTEN3 WDTEN2 WDTEN1 WDTEN0

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