ST52F510 datasheet(80/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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13 SERIAL COMMUNICATION INTERFACE

The

Serial

Communication

Interface

(SCI)

integrated into ST52F510/F513/F514 provides a

general purpose shift register peripheral, several

widely distributed devices to be linked, through

their SCI subsystem. SCI gives a serial interface

providing communication with the speed from less

than 300 up to over 115200 baud, and a flexible

character format.

SCI is a full-duplex UART-type asynchronous

system with standard Non Return to Zero (NRZ)

format for the transmitted/received bit. The length

of the transmitted word is 10/11 bits (1 start bit, 8/

9 data bits, 1 stop bit).

SCI is composed of three modules: Receiver,

Transmitter and Baud-Rate Generator.

13.1 SCI Receiver block

The

SCI

Receiver

block

manages

the

synchronization of the serial data stream and

stores the data characters. The SCI Receiver is

mainly composed of two sub-systems: Recovery

Buffer Block and SCDR_RX Block.

SCI receives data deriving from the RX pin and

drives the Recovery Buffer Block, which is a high-

speed shift register operating at a clock frequency

(CLOCK_RX) 16 times higher than the fixed baud

rate (CLOCK_TX). This sampling rate, higher than

the Baud Rate clock, detects the START condition,

Noise error and Frame error.

When the SCI Receiver is in IDLE status, it is

waiting for the START condition, which is obtained

with a logic level of 0, consecutive to a logic level

1. This condition is detected if, with the fixed

sampling time, a logic level 0 is sampled after three

logic levels of 1.

The recognition of the START bit forces the SCI

Receiver

Block

start

data

acquisition

sequence.

The data acquisition sequence is configured by the

apposite Configuration Register, allowing the

following data frame formats (see Figure 13.1):

Figure 13.1 SCI transmitted word structures

8 bit length, 1 stop bit, no parity bit

8 bit length, 2 stop bit, no parity bit

8 bit length, 1 stop bit, with parity bit

9 bit length, 1 stop bit, no parity bit

The parity bit (if used) can be configured for even

or odd parity check. If the 9-bit length format is

configured, this bit is used in transmission for the

ninth bit (see below). The ninth bit received can be

read in the R8 bit of the SCI Status Register,

address 37 (035h) bit 2 (see Figure 13.3).

Figure 13.2 SCI Block Diagram

STOP

DATA

START

STOP

DATA

START

SCI

SCDR_TX

LDPR/LDPE/LDPI

Baud-Rate

Generator

LDRI

SHIFT REGISTER

SCDR_RX

RECOVERY BUFFER

SCI Transmitter

SCI Receiver

MCLK

Program/Data

Memory

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