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ST52F510 数据表(PDF) 91 Page - STMicroelectronics |
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ST52F510 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 106 page  ST52F510/F513/F514 91/106 Figure 14.4 Event Flags and Interrupt Generation Note: The I2C interrupt events are connected to the same interrupt vector. They generate an interrupt if the corresponding Enable Control Bit (ITE) is set and the Interrupt Mask bit (MSKI2C) in the INT_MASK Configuration Register is unmasked (set to 1, see Interrupts Chapter). ADD10 BTF ADSL SB AF STOPF EVF INTERRUPT ITE * * EVF can also be set by EV6 or an error from the I2C_SR2 register. ARLO BERR Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt 10-bit Address Sent Event (Master Mode) ADD10 ITE Yes No End of Byte Transfer Event BTF Yes No Address Matched Event (Slave Mode) ADSEL Yes No Start Bit Generation Event (Master Mode) SB Yes No Acknowledge Failure Event AF Yes No Stop Detection Event (Slave Mode) STOPF Yes No Arbitration Lost Event (Multimaster configuration) ARLO Yes No Bus Error Event BERR Yes No |
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