ST52F510 datasheet(73/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Figure 12.4 PWM Mode with Reload

12.3 PWM Mode

The PWM working mode for each timer is obtained

by setting the TxMOD bit of the Configuration

The TxOUT signal in PWM Mode consists of a

signal with a fixed period, whose duty cycle can be

modified by the user.

The TxOUT period is fixed by setting the 16-bit

Prescaler bits (TxPRESC) in the PWMx_CR2 and

the 16-bit Reload value by writing the relative

Output Registers couple PWMx_RELOAD_x. The

16-bit Prescaler divides the master clock CLKM by

powers of two, determining the maximum length

period.

Reload determines the maximum value that the

counter can count before starting a new period.

The use of the two 16-bit values allows the TxOUT

period to be set with more precision when needed.

By setting the Reload value the counting resolution

decreases. In order to obtain the maximum

resolution, Reload value should be set to 0FFFFh

and the period corresponds to the one established

by the Prescaler value.

The value set in the 16-bit counter by writing the

Counter Output Registers couple, determines the

duty-cycle: when count reaches the Counter value

the TxOUT signal changes from high to low level.

The period of the PWM signal is obtained by using

the following formula:

T=PWMx-RELOAD * 2

TxPRESCTMRCLKx

where TxPRES equals the value set in the

TxPRESC bits of the PWMx_CR2 Configuration

clock that drives the Prescaler.

The duty cycle of the PWM signal is obtained by

the following formula:

Note: the PWM_x_COUNT value must be lower

than or equal to the PWM_X_RELOAD

value.

When it is equal, the TxOUT signal is always at

high level. If the Output Register PWM_x_COUNT

is 0, TxOUT signal is always at a low level.

By using a 24 MHz clock a PWM frequency that is

close to 100 Khz can be obtained.

The TIMER0 clock CLKM can also be supplied

with an external signal, applied on the TCLK pin,

which must have a frequency that is at least two

times smaller than the internal master clock.

Note: he Timers have to complete the previous

counting phase before using a new value of the

Counter. If the Counter value is changed during

counting, the new values of the timer Counter are

only used at the end of the previous counting

phase. The Counter buffer is written in two steps

(one byte per time) and is latched only after the

LSB is written. In order to avoid side effects, the

user should write the MSB before writing the LSB.

By only writing the LSB, the PWM/Timer is used as

with a 8 bit counter. The same mechanism is

applied to the two bytes of Reload but, differently

of the Counter it is set immediately. Nevertheless,

it is recommended that the Reload value be written

when the Timer is stopped in order to avoid

incongruence with the Counter value. The same

recommendation is made when reading the two

bytes of the counter: It is performed in two steps,

so if the timer is running, the carry of the LSB to the

MSB can cause the wrong 16-bit value reading. A

Reload value greater than 1 must always be used.

65535

Reload

Value

Counter

Value

PWM

Output

Ton

cycle

--------

PWMxCOUNT

PWMxRELOAD

------------------------------------------

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