ST52F510 datasheet(82/106 Pages) STMICROELECTRONICS

82 / 106 page

ST52F510/F513/F514

82/106

13.2 SCI Transmitter Block

The SCI Transmitter Block consists of the following

blocks:

SCDR_TX

and

SHIFT

synchronized, respectively, with the clock master

signal (CKM) and the CLOCK_TX.

The whole block receives the settings for the

following

transmission

modes

through

the

Configuration Register:

8 bit length, 1 stop bit, no parity bit

8 bit length, 2 stop bit, no parity bit

8 bit length, 1 stop bit, with parity bit

9 bit length, 1 stop bit, no parity bit

In case of 9 bit frame transmission, the most

significative bit arrives through the bit PAR/T8 (bit

2) of the SCI_CR1 Configuration Register. In an 8-

bit transmission, instead, this bit is used to

configure the data format: in particular to choose

the polarity control (even or odds) to implement the

parity check (see above).

After a RESET, the SCDR_TX block is in IDLE

state until it receives an enabling signal by writing

the TXSTRT bit of the SCI_CR2 Configuration

The data is loaded on the Peripheral Register

SCI_OUT (address 23 017h) by using the

instruction

LPPR,

LDPI

LDPE.

the

transmission is enabled, the data to be transmitted

transferred

from

the

Output

SCDR_TX block and the TXEM flag (bit 1) of the

SCI Status Register is reset to 0 to indicate

SCDR_TX block is full.

If the core supplies new data, this could not be

loaded in the SCDR_TX block until the current data

has not been unloaded on the Shift Register block.

Meaning that only when TXEM is 1 data can be

loaded in the SCDR_TX Block.

When the SHIFT REGISTER Block loads the data

to be transmitted on an internal buffer, the TXEND

flag (bit 0) of the SCI Status Register is reset to 0

to indicate the beginning of a new transmission. At

the end of transmission TXEND is set to 1, allowing

new data coming from SCDR_TX to be loaded in

the SHIFT REGISTER.

It is important to underline that TXEND = 1 does

not mean SCDR_TX is ready to receive a new

data. For this reason, it is better to utilize the TXEM

signal to synchronize the load instruction to the

SCI TRANSMITTER block

If the TXSTRT bit is reset, the transmission is

stopped, but the SCI Transmitter block completes

the transmission in progress before resetting.

13.3 Baud Rate Generator Block

The Baud Rate Generator Block performs the

division of the clock master signal (CKM) in a set of

synchronism

frequencies

for

the

serial

bit

reception/transmission on the external line.

Reception frequency (CLOCK_RX) is 16 times

higher

than

the

transmission

frequency

(CLOCK_TX).

To adapt the Baud Rate Generator to the clock

master frequency supplied by the user, a 12-bit

Prescaler must be programmed by loading the

Configuration Registers SCI_CR2 (PRESC_H bit

11:8 of the 12 bit prescaler) and SCI_CR3

(PRESC_L bit 7:0 of the 12 bit prescaler). The

prescaler allows the programming of all standard

Baud Rates by using the most common clock

master sources.

The Prescaler value can be obtained by the

following formula:

Where CKM is the clock master frequency

(expressed in Hz) and BAUD is the desired Baud

Rate (expressed in bit/second). The obtained

value is rounded to the nearest integer value. This

rounding can cause an error in the obtained Baud

Rate. This error must be lower than 3%. To verify

that the PRESC value satisfies this constrain, the

obtained Baud Rate must be computed by

inverting the previous formula:

then the following relation can be used to verify

that the difference with the desired Baud Rate is

lower than 3%:

Table 13.1 shows the recommended Prescaler

values for common clock master frequencies. To

get more precision in Baud Rate, standard quartz

frequencies for serial communication can be used.

The corresponding Prescaler values for these

frequencies are showed in the Table 13.2.

PRESC

round

CKM

BAUD

-----------------------------





BAUD

CKM

PRESC

-------------------------------

BAUD

–

BAUD

-------------------------------------------

0.03

ST52F510 数据表(PDF) 82 Page - STMicroelectronics

ST52F510 数据表(HTML) 82 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ST52F510 数据表(PDF) 82 Page - STMicroelectronics

ST52F510 数据表(HTML) 82 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载