ST52F510 datasheet(41/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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5.3 Interrupt Sources

ST52F510/F513/F514 manages interrupt signals

generated by the internal peripherals or generated

by software by the TRAP instruction or coming

from the Port pins. There are two kinds of

interrupts coming from the Port pins: the NMI and

the Ports Interrupts.

NMI (Not Maskable Interrupt) is associated with pin

PA7 when it is configured as Alternate Function.

This interrupt source doesn’t have a configurable

level priority and cannot be masked. The fixed

priority level is lower than the software TRAP and

higher than all the other interrupts. The NMI can be

configured to be active on the rising or the falling

edge.

The Port Interrupts sources are connected with

Port A and Port B pins. The pins belonging to the

same Port are associated with the same interrupt

vector: there is one vector for Port A and one for

Port B. In order to use one port pin as interrupt, it

must be configured as an interrupt source (see I/O

Ports chapter). In this manner, up to 16 Port

Interrupt sources are available. By reading the Port

the sources that belong to the same Port can be

discriminated.

The

Port

Interrupts

can

configured to be active on the rising or the falling

edge.

Warning: changing the NMI or Port Interrupt

polarity an interrupt request is generated.

All the interrupt sources are filtered, in order to

avoid false interrupt requests caused by glitches.

The Trap instruction is something between a

interrupt and a call: it generated an interrupt

request at top priority level and the control is

passed to the associated interrupt routine which

vector is located in the fixed addresses 30-32. This

routine cannot be interrupted and it is serviced

even if the interrupts are globally disabled.

Note: Similarly to the CALL instruction, after a

TRAP the flags are not stacked.

Figure 5.3 Example of Interrupt Requests

5.4 Interrupt Maskability and Priority Levels

Interrupts can be masked by the corresponding

INT_MASK Configuration Register

0 (00h). An

interrupt is enabled when the mask bit is “1". Vice

versa, when the bit is “0”, the interrupt is masked

and the eventual requests are kept pending.

All the interrupts, with the exception of the NMI and

TRAP that have fixed level priority, have a

configurable priority level. The configuration of the

priority levels is completed by writing three

consecutive Configuration Registers: INT_PRL_H,

INT_PRL_M, INT_PRL_L, addresses from 2 to 4

(02h-04h). The 24 bits of these registers are

divided into 8 groups of three bits: each group is

associated with a priority level. The three bits of

each group are written with the code number

associated with the interrupt source. See Table 5.1

to know the codes.

Remark:

The

priority

levels

Configuration

Registers must be programmed with different

values for each 3-bit groups to avoid erroneous

operation. For this reason the Interrupt priority

must be fixed at the beginning of the main

program, because

the

reset

values of

the

Configuration

Registers

correspond

undefined

configuration

(all

zeros).

During

program execution the interrupt priority can only be

modified within the Main Program: it cannot be

changed within an interrupt service routine.

5.5 Interrupt RESET

When an interrupt is masked, all requests are not

acknowledged and remain pending. When the

pending interrupt is enabled it is immediately

serviced. This event may be undesired; in order to

avoid this

a RINT instruction may be inserted

followed by the code number that identifies the

interrupt to reset the pending request. See Table

5.1 to know the codes.

MAIN PROGRAM

INT2

INT0

INT2

INT1

INT2

INT3

INT4

MAIN PROGRAM

PRIORITY

LEVEL

INT2

INT0

INT4

INT1

INT3

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