ST52F510 datasheet(24/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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When a return occurs (RET or RETI instruction),

the SSP is increased by 2 and the data stored in

the pointed locations couple is restored back into

the PC.

The current SSP can be read and write in the

couple of Configuration Registers 44 02Ch (MSB:

page number, always 32 020h) and 45 02Dh (LSB:

location address) (see Figure 3.3). In ST52F510/

F513/F514 the user can only consider the LSB

because the MSB is always the same.

The User Stack is used to store user data and is

located beginning from a RAM bench location set

by the user (USTP) by writing the couple of

Configuration Registers 5 005h (MSB: page

number) and 6 005h (LSB: location address) (see

Figure 3.3). Register 5, which is the page number,

must always be set to a value between 32 (020h)

and 255 (0FFh): values higher than 32 always

address RAM on page 32.

Note: In ST52F510/F513/F514 MSB doesn’t have

to be set or read because the RAM is only 256

bytes. The LSB of the user stack is equal to 0 at

reset. The LSB of the system stack is equal to 255

at reset.

This feature allows a flexible use of the User Stack

in terms of dimension and to avoid overlaps. The

User Stack Pointer (USP) points to the first

currently available stack location. When the user

stores a byte value contained in the Register File

by using the PUSH instruction, the value is stored

in the position pointed to by the USP that is

increased (the User Stack order is opposite to the

System Stack one). When the user takes a value

from the User Stack with the POP instruction, the

USP is decreased and the value pointed to is

copied in the specified Register File location.

By writing the USTP, the new address is

automatically written in the USP. The current USP

can be read from the Input

Registers 11 0Bh

(MSB: page number, always 32 020h) and 12 0Ch

(LSB: location address) (see Figure 3.3). In

ST52F510/F513/F514 the user can only consider

the LSB because the MSB is always the same.

Note: The user must pay close attention to avoid

overlapping user and Stacks data. The User Stack

Top location and the System Stack Pointer should

be configured with care in order to have enough

space between the two stacks.

3.5 Input Registers

The ST52F510/F513/F514 Input Registers bench

consists of a file of 8-bit registers containing data

or the status of the peripherals. For example, the

Input Registers contain data converted by the

ADC,

Ports, serial communication peripherals,

Timers, etc.

The Input Registers can be accessed by using the

LDRI instruction that loads the specified Register

File address with the contents of the specified

Input Register. See the Programming Manual for

further details on this instruction. The Input

Registers are read-only registers.

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Input Registers is shown in Table 3.1.

3.6 Output registers

The

ST52F510/F513/F514

Output

Registers

bench consists of a file of 8-bit registers containing

data sent to the Peripherals and the I/O Ports (for

example: Timer Counters, data to be transmitted

by the serial communication peripherals, data to be

sent to the Port pins in output, etc.).

The registers are located inside the Peripherals

and Ports, which allow flexibility and modularity in

the design of new family devices.

The Output Registers are write only. In order to

access the configuration Register the user can use

the following instructions:

LDPI: loads the immediate value in the specified

Output Register.

LDPR: loads the contents of the specified

specified. This instruction allows computed data

to be sent to Peripherals and Ports.

LDPE direct: loads the contents of the specified

Program/Data Memory location into the output

be sent to Peripherals and Ports from a table.

LDPE indirect: loads the contents of the

Program/Data Memory location whose address

is contained in the specified Register File

location into the output register specified. This

instruction allows data to be sent to Peripherals

and Ports from a table pointed to by a register.

See the Programming manual for further details

about these instructions.

In order to simplify the concept, a mnemonic name

is assigned to each register. The same name is

used in Visual FIVE development tools. The list of

the Output Registers is shown in Table 3.2.

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