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ST52F510 数据表(PDF) 42 Page - STMicroelectronics

部件名 ST52F510
功能描述  8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
PDF  106 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST52F510 数据表(HTML) 42 Page - STMicroelectronics

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5.6 Register Description
Interrupt Mask Register (INT_MASK)
Configuration Register 0 (00h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: MSKPB Interrupt Mask Port B
0: Port B interrupt masked
1: Port B interrupt enabled
Bit 6: MSKPA Interrupt Mask Port A
0: Port A interrupt masked
1: Port A interrupt enabled
Bit 5: MSKI2C Interrupt Mask I2C Interface
0: I2C Interface interrupt masked
1: I2C Interface interrupt enabled
Bit 4: MSKSPI Interrupt Mask SPI
0: SPI interrupt masked
1: SPI interrupt enabled
Bit 3: MSKSCI Interrupt Mask SCI
0: SCI interrupt masked
1: SCI interrupt enabled
Bit 2: MSKT1 Interrupt Mask PWM/Timer 1
0: Pwm/Timer 1 interrupt masked
1: Pwm/Timer 1 interrupt enabled
Bit 1: MSKT0 Interrupt Mask Pwm/Timer 0
0: Pwm/Timer 0 interrupt masked
1: Pwm/Timer 0 interrupt enabled
Bit 0: MSKAD Interrupt Mask A/D Converter
0: A/D interrupt masked
1: A/D interrupt enabled
Interrupt Polarity Register (INT_POL)
Configuration Register 1 (01h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7-5: Not Used
Bit 4-3: See Timer 0 Registers Description
Bit 2: POLPB Port B Interrupt Polarity
0: The Port B interrupt is triggered on the
rising edge of the applied external signal.
1: The Port B interrupt is triggered on the
falling edge of the applied external signal.
Bit 1: POLPA Port A Interrupt Polarity
0: The Port A interrupt is triggered on the
rising edge of the applied external signal.
1: The Port A interrupt is triggered on the
falling edge of the applied external signal.
Bit 0: POLNMI Non Maskable Interrupt Polarity
0: The NMI is triggered on the rising edge of
the applied external signal.
1: The NMI is triggered on the falling edge of
the applied external signal.
High Priority Register (INT_PRL_H)
Configuration Register 2 (02h) Read/Write
Reset Value: 1111 1010 (0FAh)
Medium Priority Register (INT_PRL_M)
Configuration Register 3 (03h) Read/Write
Reset Value: 1100 0110 (0C6h)
70
MSKPB
MSKPA MSKI2C MSKSPI MSKSCI MSKT1
MSKT0
MSKAD
70
-
-
-
RESPOL STRPOL POLPB
POLPA POLNMI
70
PRL23
PRL22
PRL21
PRL20
PRL19
PRL18
PRL17
PRL16
70
PRL15
PRL14
PRL13
PRL12
PRL11
PRL10
PRL9
PRL8



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