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ST52F510 数据表(PDF) 31 Page - STMicroelectronics |
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ST52F510 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 106 page  ST52F510/F513/F514 31/106 4 MEMORY PROGRAMMING ST52F510/F513/F514 provides an on-chip user programmable non-volatile memory, which allows fast and reliable storage of user data. Program/Data Memory addressing space is composed by a Single Voltage Flash Memory and a RAM memory bench. The ST52F513/514 devices also have a Data EEPROM bench to store permanent data with long term retention and a high number of write/erase cycles. All the Program Data memory addresses can execute code, including RAM and EEPROM benches. The memory is programmed by setting the Vpp pin equal to Vdd. Data and commands are transmitted through the I2C serial communication protocol. The same procedure is used to perform “In-Situ” the programming of the device after it is mounted in the user system. Data can also be written in run- time with the In-Application Programming (IAP). The Memory can be locked by the user during the programming phase, in order to prevent external operation such as reading the program code and assuring protection of user intellectual property. Flash and EEPROM pages can be protected by unintentional writings. Remark: the memory contents are protected by the Error Correction Code (ECC) algorithm that uses a 4-bit redundancy to correct one bit errors. Warning: when entering the ISP, the default values for Option Bytes are considered, so a Voltage Supply higher than the PLVD lower threshold must be applied to program the device. 4.1 Program/Data Memory Organization The Program/Data Memory is organized as described in Section 3.3. The various sales types have different amounts of each type of memory. Table 4.1 describes the memory benches amount and page allocation for each sales type. The addressing spaces are organized in pages of 256 bytes. Each page is composed by blocks of 32 bytes. Memory programming is performed one block at a time in order to speed-up the programming time (about 2.5 ms per block). The whole location address is composed as follows: 15 87 54 0 Page address Block address address inside the block Table 4.1 Sales Type Memory Organization Device Flash Memory RAM Memory EEPROM Memory Amount Pages Amount Page Amount Page(s) ST52F510c2p6 4096 bytes 0 to 15 256 bytes 32 - - ST52F510c3p6 8192 bytes 0 to 31 256 bytes 32 - - ST52F513c2p6 3840 bytes 0 to 14 256 bytes 32 256 bytes 15 ST52F513c3p6 7936 bytes 0 to 30 256 bytes 32 256 bytes 31 ST52F514c1p6 4096 bytes 0 to 15 256 bytes 32 1024 bytes 16-19 ST52F514c3p6 4096 bytes 0 to 15 256 bytes 32 4096 bytes 16-31 legend: c: Y=16 pins, F=20 pins, G=28 pins, K=32/34 pin p: B=DIP, M=SO, T=TQFP |
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