ST52F510 datasheet(93/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

93/106

1: Standard I2C Mode (recommended up to

100 kHz)

0: Fast I2C Mode (recommended up to 400

kHz)

Bit 6-0: CC6-CC0 7-bit clock divider

These bits select the speed of the bus (FSCL)

depending on the I2C mode. They are not

cleared when the interface is disabled

(PE=0). The speed can be computed as

follows:

– Standard mode (FM/SM=1): FSCL <= 100kHz

FSCL = fCPU/(3x[CC6..CC0]+11)

– Fast mode (FM/SM=0): FSCL > 100kHz

FSCL = fCPU/(2x[CC6..CC0]+9)

Warning: For safety reason, CC6-CC0 bits must

be configured with a value >= 3 for the Standard

mode and >=2 for the Fast mode.

I2C Own Address Register 1 (I2C_OAR1)

Configuration Register 18 (012h) Read/Write

Reset Value: 0000 0000 (00h)

7-bit Addressing Mode

bit 7-1: ADD7-ADD1 Interface address.

These bits define the I2C bus address of the

interface. They are not cleared when the

interface is disabled (PE=0).

Bit 0: ADD0

Address direction bit.

This

bit

“don’t

care”,

the

interface

acknowledges either 0 or 1. It is not cleared

when the interface is disabled (PE=0).

Note: Address 01h is always ignored.

10-bit Addressing Mode

bit 7-0: ADD7-ADD0 Interface address.

These are the least significant bits of the I2C

bus address of the interface. They are not

cleared when the interface is disabled

(PE=0).

I2C Own Address Register 2 (I2C_OAR2)

Configuration Register 19 (013h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7-3: Not Used

bit 7-1: ADD8-ADD8 Interface address.

These are the most significant bits of th I2C

bus address of the interface (10-bit mode

only). They are not cleared when the

interface is disabled (PE=0).

Bit 0: Reserved

14.5.2 I2C Interface Input Registers.

I2C Data Input Register (I2C_IN)

Input Register 6 (06h) Read only

Reset Value: 0000 0000 (00h)

bit 7-0: I2CDI7-I2CDI0 Received data.

These bits contain the byte to be received from the

bus in Receiver mode: the first data byte is

received automatically in the I2C_IN register using

the least significant bit of the address.

Then, the next data bytes are received one by one

after reading the I2C_IN register.

I2C Status Register 1 (I2C_SR1)

Input Register 7 (07h) Read only

Reset Value: 0000 0000 (00h)

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

---

ADD9

ADD8

I2CDI7

I2CDI6

I2CDI5

I2CDI4

I2CDI3

I2CDI2

I2CDI1

I2CDI0

EVF

ADD10

TRA

BUSY

BTF

ADSL

M/SL

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