ST52F510 datasheet(60/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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9 INSTRUCTION SET

ST52F510/F513/F514 supplies 107 (98 + 9 Fuzzy)

instructions that perform computations and control

the device. Computational time required for each

instruction consists of one clock pulse for each

Cycle plus 2 clock pulses for the decoding phase.

Total computation time for each instruction is

reported in Table 9.1

The ALU of ST52F510/F513/F514 can perform

multiplication

(MULT)

and

division

(DIV).

Multiplication is performed by using 8 bit operands

storing the result in 2 registers (16 bit values), see

Figure 2.3.

Division is performed between a 16 bit dividend

and an 8 bit divider, the result and the remainder

are stored in two 8-bit registers (see Figure 2.4).

9.1 Addressing Modes

ST52F510/F513/F514

instructions

allow

the

following addressing modes:

Inherent: this instruction type does not require

an operand because the opcode specifies all the

information necessary to carry out the

instruction. Examples: NOP, SCF.

Immediate: these instructions have an operand

as a source immediate value. Examples: LDRC,

ADDI.

Direct: the operands of these instructions are

specified with the direct addresses. The

operands can refer (according to the opcode) to

addresses belonging to the different addressing

spaces. Example: SUB, LDRE.

Indirect: data addresses that are required are

found in the locations specified as operands.

Both source and/or destination operands can be

addressed indirectly. The operands can refer,

(according to the opcode) to addresses

belonging to different addressing spaces.

Examples: LDRR(reg1),(reg2);

LDER mem_addr,(reg1).

Bit Direct: operands of these instructions directly

address the bits of the specified Register File

locations. Examples: BSET, BTEST.

9.2 Instruction Types

ST52F510/F513/F514

supplies

the

following

instruction types:

Load Instructions

Arithmetic and Logic Instructions

Bitwise instructions

Jump Instructions

Interrupt Management Instructions

Control Instructions

The instructions are listed in Table 9.1

Table 9.1 Instruction Set

Load Instructions

Mnemonic

Instruction

Bytes

Cycles

BLKSET

BLKSET const

(*)

GETPG

GETPG regx

LDCE

LDCE confx,memy

8/9

LDCI

LDCI confx, const

LDCNF

LDCNF regx, conf

LDCR

LDCR confx, regy

LDER

LDER memx, regy

LDER

LDER (regx),(regy)

LDER

LDER (regx), regy

LDER

LDER memx,(regy)

LDFR

LDFR fuzzyx, regy

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