ST52F510 datasheet(99/106 Pages) STMICROELECTRONICS

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is taking place with an external device. When this

occurs, the transfer continues uninterrupted; and

the software writing will be unsuccessful.

Write collisions can occur both in master and slave

mode.

Note: a “read collision” will never occur since the

data byte received is placed in a buffer, in which

access is always synchronous with the ICU

operation.

In Slave mode

When the CPHA bit is set:

The slave device will receive a clock (SCK) edge

prior to the latch of the first data transfer. This first

clock edge will freeze the data in the slave device

SPI_OUT register and output the MSBit on to the

external MISO pin of the slave device.

The SS pin low state enables the slave device, but

the output of the MSBit onto the MISO pin does not

take place until the first data transfer clock edge

occurs.

When the CPHA bit is reset:

Data is latched on the occurrence of the first clock

transition. The slave device doesn’t have a way of

knowing when that transition will occur; therefore,

the slave device collision occurs when software

attempts to write the SPI_OUT register after its SS

pin has been pulled low.

For this reason, the SS pin must be high, between

each data byte transfer, in order to allow the CPU

to write in the SPI_OUT register without generating

a write collision.

In Master mode

Collision in the master device is defined as a write

of the SPI_OUT register, while the internal serial

clock (SCK) is in the process of transfer.

The SS pin signal must always be high on the

master device.

Figure 15.3 CHPA/SS Timing Diagram

WCOL bit

The WCOL bit in the SPI_STATUS_CR register is

set if a write collision occurs.

No SPI interrupt is generated when the WCOL bit

is set (the WCOL bit is a status flag only).

The WCOL bit is cleared by a software sequence

(see Section 15.5).

15.4.5 Master Mode Fault.

Master mode fault occurs when the master device

has its SS pin pulled low, then the MODF bit is set.

Master mode fault affects the SPI peripheral in the

following ways:

– The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

– The SPE bit is reset. This blocks all output from

the device and disables the SPI peripheral.

– The MSTR bit is reset, forcing the device into

slave mode.

Clearing the MODF bit is done through a software

sequence:

1. A read or write access to the SPI_STATUS_CR

2. A write to the SPI_CR register.

Note: To avoid any multiple slave conflicts in the

case of a system comprising several MCUs, the

pin must be pulled high during the clearing

sequence of the MODF bit. The SPE and MSTR

bits may be restored to their original state during or

after this clearing sequence.

Hardware does not allow the user to set the SPE

and MSTR bits, while the MODF bit is set (except

in the MODF bit clearing sequence).

In a slave device the MODF bit can’t be set, but in

a multi master configuration the device can be in

slave mode with this MODF bit set.

The MODF bit indicates that there might have been

a multi-master conflict for system control and

allows a proper exit from system operation to a

reset or default system state using an interrupt

routine.

MOSI/MISO

Master SS

Slave SS

(CPHA=0)

Slave SS

(CPHA=1)

Byte 1

Byte 2

Byte 3

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