ST52F510 datasheet(103/106 Pages) STMICROELECTRONICS

103 / 106 page

ST52F510/F513/F514

103/106

15.5 SPI Register Description

In the following sections describe the registers

used by the SPI.

15.5.1 SPI Configuration Registers.

SPI Control Register (SPI_CR)

Configuration Register 20 (014h) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7: SPIE Serial peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever

SPIF=1 or MODF=1 in SPI_STATUS_CR

Bit 6: SPE Serial peripheral output enable.

This bit is set and cleared by software. It is

also cleared by hardware when, in master

mode, SS=0 (see Section 15.4.5 Master

Mode Fault).

0: I/O port connected to pins

1: SPI alternate functions connected to pins

Note: The SPE bit is cleared by reset, so the SPI

peripheral is not initially connected to the pins.

Bit 5: SPR2 Divider Enable.

This bit is set and cleared by software and it

is cleared by reset. It is used with the

SPR[1:0] bits to set the baud rate. Refer to

Table 15.1.

0: Divider by 2 enabled

1: Divider by 2 disabled

Note: This bit has no effect in slave mode.

Bit 4: MSTR Master/Slave mode select.

This bit is set and cleared by software. It is

also cleared by hardware when, in master

mode, SS=0 (see Section 15.4.5 Master

Mode Fault).

0: Slave mode is selected

1: Master mode is selected, the function of

the SCK pin changes from an input to an

output and the functions of the MISO and

MOSI pins are reversed.

Bit 3: CPOL Clock polarity.

This bit is set and cleared by software. This

bit determines the steady state of the serial

Clock. The CPOL bit affects both the master

and slave modes.

0: The steady state is a low value at the SCK

pin.

1: The steady state is a high value at the SCK

pin.

Note: SPI must be disabled by resetting the SPE

bit if CPOL is changed at the communication byte

boundaries.

Bit 2: CPHA Clock phase.

This bit is set and cleared by software.

0: The first clock transition is the first data

capture edge.

1: The second clock transition is the first

capture edge.

Bit 1-0: SPR1-SPR0 Serial peripheral rate.

These bits are set and cleared by software.

Used with the SPR2 bit, they select one of six

baud rates to be used as the serial clock

when the device is a master (see Table 15.1).

These 2 bits have no effect in slave mode.

Remark: It is recommended to write the SPI_CR

working in master mode, vice versa when working

in slave mode.

SPI Control-Status Register (SPI_STATUS_CR)

Configuration Register 21 (015h) Read/Write

Reset Value: 0000 0000 (00h)

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Table 15.1 Serial Peripheral Baud Rate

Serial Clock

SPR2

SPR1

SPR0

fCKM/2

100

fCKM/4

000

fCKM/8

001

fCKM/16

110

fCKM/32

010

fCKM/64

011

SPIF

WCOL

MODF

SOD

SSM

SSI

ST52F510 数据表(PDF) 103 Page - STMicroelectronics

ST52F510 数据表(HTML) 103 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载