ST52F510 datasheet(89/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Slave address transmission

At this point, the slave address is sent to the SDA

line via the internal shift register.

In 7-bit addressing mode, one address byte is sent.

In 10-bit addressing mode, sending the first byte

including

the

header

sequence

causes

the

following event:

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_OUT register, holding the SCL line low (see

Figure 14.3 Transfer sequencing EV9).

The second address byte is sent by the interface.

After completion of this transfer (and acknowledge

from the slave if the ACK bit is set):

– The EVF bit is set by hardware with interrupt

generation if the ITE bit is set.

Afterwards, the master waits for a read of the

I2C_SR1 register followed by a write in the

I2C_CR register (for example set PE bit), holding

the SCL line low (see Figure 14.3 Transfer

sequencing EV6).

Next,

the

master

must

enter

Receiver

Transmitter mode.

Note: In 10-bit addressing mode, in order to switch

the master to Receiver mode, software must

generate a repeated Start condition and resend the

header sequence with the least significant bit set

(11110xx1).

Master Receiver

Following the address transmission and after

I2C_SR1

and I2C_CR

registers

have

been

accessed, the master receives bytes from the SDA

line into the I2C_IN register via the internal shift

sequence:

– Acknowledge pulse if the ACK bit is set

– EVFand BTF bits are set by hardware with an in-

terrupt if the ITE bit is set.

Afterwards, the interface waits for a read of the

I2C_SR1 register followed by a read of the I2C_IN

14.3 Transfer sequencing EV7).

In order to close the communication: before

reading the last byte from the I2C_IN register, set

the STOP bit to generate the Stop condition. The

interface automatically goes back to slave mode

(M/SL bit cleared).

Note: In order to generate the non-acknowledge

pulse after the last data byte received, the ACK bit

must be cleared just before reading the second last

data byte.

Master Transmitter

Following the address transmission and after the

I2C_SR1 register has been read, the master sends

bytes from the I2C_OUT register to the SDA line

via the internal shift register.

The master waits for a read of the I2C_SR1

14.3 Transfer sequencing EV8).

When the acknowledge bit is received, the

interface sets:

– EVF and BTF bits with an interrupt if the ITE bit

is set.

In order to close the communication: after writing

the last byte to the I2C_OUT register, set the

STOP bit to generate the Stop condition. The

interface automatically returns to slave mode (M/

SL bit cleared).

Error Cases

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the EVF and

BERR bits are set by hardware with an interrupt

if ITE is set.

– AF: Detection of a non-acknowledge bit. In this

case, the EVF and AF bits are set by hardware

with an interrupt if the ITE bit is set. To resume,

set the START or STOP bit.

– ARLO: Detection of an arbitration lost condition.

In this case the ARLO bit is set by hardware

(with an interrupt if the ITE bit is set and the in-

terface automatically goes back to slave mode

(the M/SL bit is cleared).

Note: In all these cases, the SCL line is not held

low; however, the SDA line can remain low due to

possible «0» bits transmitted last. Both lines must

be released via software.

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