ST52F510 datasheet(77/106 Pages) STMICROELECTRONICS

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ST52F510/F513/F514

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Bit 7-0: T0CO7-0 PWM/Timer 0 Counter MSB

This register is used to write the Timer 0 Counter

value (LSB).

Note:

writing

this

the

PWM0_COUNT_OUT_x couple is latched in the

internal registers of the peripherals. For this

reason, this register should be written after the

MSB one.

PWM/Timer 0 Reload High Output Register

(PWM0_RELOAD_H)

Output Register 9 (09h) Write only

Reset Value: 1111 1111 (0FFh)

Bit 7-0: T0REL15-8 PWM/Timer 0 Reload MSB

This register is used to write the Timer 0 Reload

value (MSB).

Note: this register is latched after writing the LSB

part (PWM0_RELOAD_L: see below). For this

reason, this register must be written before the

LSB.

PWM/Timer 0 Reload Low Output Register

(PWM0_RELOAD_L)

Output Register 10 (0Ah) Write only

Reset Value: 1111 1111 (0FFh)

Bit 7-0: T0REL7-0 PWM/Timer 0 Reload LSB

This register is used to write the Timer 0 Reload

value (LSB).

Note:

writing

this

the

PWM0_RELOAD_x couple is latched in the

internal registers of the peripherals. For this reason

this register should be written after the MSB one.

12.6 PWM/Timer 1 Register Description

The following registers are related to the use of the

PWM/Timer 1.

12.6.1 PWM/Timer 1 Configuration Registers.

PWM/Timer 1 Control Register 1 (PWM1_CR1)

Configuration Register 12 (0Ch) Read/Write

Reset Value: 0000 0000 (00h)

Bit 7: T1MOD PWM/Timer 1 Mode

0: Timer Mode

1: PWM Mode

Bit 6: T1IES Interrupt on Stop signal Enable

0: interrupt disabled

1: interrupt enabled

Bit 5: T1IEF Interrupt on T1OUT falling Enable

0: interrupt disabled

1: interrupt enabled

Bit 4: T1IER Interrupt on T1OUT rising Enable

0: interrupt disabled

1: interrupt enabled

Bit 3: not used

Bit 2: T1STRT PWM/Timer 1 Start bit

0: Timer 0 stopped

1: Timer 0 started

Bit 1: not used

Bit 0: T1RES PWM/Timer 1 Reset bit

0: PWM/Timer 0 reset

1: PWM/Timer 0 set

T0REL15 T0REL14 T0REL13 T0REL12 T0REL11 T0REL10 T0REL9 T0REL8

T0REL7 T0REL6 T0REL5 T0REL4 T0REL3 T0REL2 T0REL1 T0REL0

T1MOD

T1IES

T1IEF

T1IER

T1STRT

T1RES

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