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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST52F510 数据表(PDF) 70 Page - STMicroelectronics |
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ST52F510 数据表(HTML) 70 Page - STMicroelectronics |
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70 / 106 page  ST52F510/F513/F514 70/106 Watchdog Control Register (WDT_CR) Configuration Register 7 (07h) Read/Write Reset Value: 0000 0001 (00h) Bit 7-4: Not Used Bit 3-0: D3-0 Watchdog Clock divisor factor bits The Watchdog Clock (WDT CLK) is divided by the numeric factor determined by these bits, according with Table 11.2 and the following formula: 70 -- -- D3 D2 D1 D0 Timeout ms () 510 5 DivisionFactor × × Clock MHz () ----------------------------------------------------------------- = Table 11.2 Watchdog Timeout configuration examples WDT_CR(3:0) Division Factor Timeout Values (ms) 5 MHz 10 MHz 20MHz 0000 1 0.1 0.05 0.025 0001 625 62.5 31.25 15.625 0010 1250 125 62.5 31.25 0011 1875 187.5 93.75 46.875 0100 2500 250 125 62.5 0101 3125 312.5 156.25 78.125 0110 3750 375 187.5 93.75 0111 4375 437.5 218.75 109.375 1000 5000 500 250 125 1001 5625 562.5 281.25 140.625 1010 6250 625 312.5 156.25 1011 6875 687.5 343.75 171.875 1100 7500 750 375 187.5 1101 8125 812.5 406.25 203.125 1110 8750 875 437.5 218.75 1111 9375 937.5 468.75 234.375 |
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